it83xx: IT8320 DX version compatibility

[espi]:
  The supported maximum frequency of slave is adjustable and we
  set it at 66MHz at initialization (the same as Bx version).
[gpio]:
  All GPIOs support interrupt on rising, falling, and either edge.
  More GPIOs support 1.8v input.
[irq]:
  Enable newly added interrupts.
[registers]:
  Remove unused declaration.
[system]:
  Watchdog reset supports resetting the full EC domain function
  (include write protect setting).

BUG=none
BRANCH=none
TEST=[espi]:
      Ensure the eSPI frequency is able to work at 50 MHz on small
      core CPU.
     [gpio]:
      The settings of input voltage 1.8v selection and both edge interrupt
      registers are matched to the declarations of GPIO signal in gpio.inc.
     [system]:
      The console command "reboot hard" is able to unprotected the flash.
      (testing failed)

Change-Id: I053d8a59a9e90d28e2f2c9b79675ea84425f4959
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1113166
Reviewed-by: Jett Rink <jettrink@chromium.org>

6 files changed, 244 insertions, 49 deletions

diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h
index 5e7a501a8f..334fbbdedd 100644
--- a/chip/it83xx/config_chip.h
+++ b/chip/it83xx/config_chip.h
@@ -64,11 +64,31 @@
  */
 #define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_ERASE_SIZE
 
+#if defined(CHIP_VARIANT_IT8320BX)
 /* This is the physical size of the flash on the chip. We'll reserve one bank
  * in order to emulate per-bank write-protection UNTIL REBOOT. The hardware
  * doesn't support a write-protect pin, and if we make the write-protection
  * permanent, it can't be undone easily enough to support RMA. */
 #define CONFIG_FLASH_SIZE  0x00040000
+#elif defined(CHIP_VARIANT_IT8320DX)
+#define CONFIG_FLASH_SIZE  0x00080000
+/* The slave frequency is adjustable (bit[2-0] at register IT83XX_ESPI_GCAC1) */
+#define IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE
+/* Watchdog reset supports hardware reset. */
+/* TODO(b/111264984): watchdog hardware reset function failed. */
+#undef IT83XX_ETWD_HW_RESET_SUPPORT
+/*
+ * More GPIOs can be set as 1.8v input.
+ * Please refer to gpio_1p8v_sel[] for 1.8v GPIOs.
+ */
+#define IT83XX_GPIO_1P8V_PIN_EXTENDED
+/* All GPIOs support interrupt on rising, falling, and either edge. */
+#define IT83XX_GPIO_INT_FLEXIBLE
+/* Enable interrupts of group 21 and 22. */
+#define IT83XX_INTC_GROUP_21_22_SUPPORT
+#else
+#error "Unsupported chip variant!"
+#endif
 
 /****************************************************************************/
 /* Define our flash layout. */
diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c
index 5f6d48f6b1..c31326f386 100644
--- a/chip/it83xx/espi.c
+++ b/chip/it83xx/espi.c
@@ -528,6 +528,17 @@ void espi_interrupt(void)
 
 void espi_init(void)
 {
+	/*
+	 * bit[2-0], the maximum frequency of operation supported by slave:
+	 * 000b: 20MHz
+	 * 001b: 25MHz
+	 * 010b: 33MHz
+	 * 011b: 50MHz
+	 * 100b: 66MHz
+	 */
+#ifdef IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE
+	IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | (1 << 2);
+#endif
 	/* reset vw_index_flag at initialization */
 	espi_reset_vw_index_flags();
 
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
index fc533a5c67..ee1271f694 100644
--- a/chip/it83xx/gpio.c
+++ b/chip/it83xx/gpio.c
@@ -62,6 +62,27 @@ static volatile uint8_t *wuemr(uint8_t grp)
 			(volatile uint8_t *)(IT83XX_WUC_WUEMR5 + 4*(grp-5));
 }
 
+/**
+ * Convert wake-up controller (WUC) group to the corresponding wake-up both edge
+ * mode register (WUBEMR). Return pointer to the register.
+ *
+ * @param grp  WUC group.
+ *
+ * @return Pointer to corresponding WUBEMR register.
+ */
+#ifdef IT83XX_GPIO_INT_FLEXIBLE
+static volatile uint8_t *wubemr(uint8_t grp)
+{
+	/*
+	 * From WUBEMR1-WUBEMR4, the address increases by ones. From WUBEMR5 on
+	 * the address increases by fours.
+	 */
+	return (grp <= 4) ?
+			(volatile uint8_t *)(IT83XX_WUC_WUBEMR1 + grp-1) :
+			(volatile uint8_t *)(IT83XX_WUC_WUBEMR5 + 4*(grp-5));
+}
+#endif
+
 /*
  * Array to store the corresponding GPIO port and mask, and WUC group and mask
  * for each WKO interrupt. This allows GPIO interrupts coming in through WKO
@@ -84,6 +105,11 @@ static const struct {
 	[IT83XX_IRQ_WKO22] =    {GPIO_C, (1<<4),        2, (1<<2)},
 	[IT83XX_IRQ_WKO23] =    {GPIO_C, (1<<6),        2, (1<<3)},
 	[IT83XX_IRQ_WKO24] =    {GPIO_D, (1<<2),        2, (1<<4)},
+#ifdef IT83XX_GPIO_INT_FLEXIBLE
+	[IT83XX_IRQ_WKO40] =    {GPIO_E, (1<<5),        4, (1<<0)},
+	[IT83XX_IRQ_WKO45] =    {GPIO_E, (1<<6),        4, (1<<5)},
+	[IT83XX_IRQ_WKO46] =    {GPIO_E, (1<<7),        4, (1<<6)},
+#endif
 	[IT83XX_IRQ_WKO50] =    {GPIO_K, (1<<0),        5, (1<<0)},
 	[IT83XX_IRQ_WKO51] =    {GPIO_K, (1<<1),        5, (1<<1)},
 	[IT83XX_IRQ_WKO52] =    {GPIO_K, (1<<2),        5, (1<<2)},
@@ -151,6 +177,12 @@ static const struct {
 	[IT83XX_IRQ_WKO120] =   {GPIO_I, (1<<1),        13, (1<<0)},
 	[IT83XX_IRQ_WKO121] =   {GPIO_I, (1<<2),        13, (1<<1)},
 	[IT83XX_IRQ_WKO122] =   {GPIO_I, (1<<3),        13, (1<<2)},
+#ifdef IT83XX_GPIO_INT_FLEXIBLE
+	[IT83XX_IRQ_WKO123] =   {GPIO_G, (1<<3),        13, (1<<3)},
+	[IT83XX_IRQ_WKO124] =   {GPIO_G, (1<<4),        13, (1<<4)},
+	[IT83XX_IRQ_WKO125] =   {GPIO_G, (1<<5),        13, (1<<5)},
+	[IT83XX_IRQ_WKO126] =   {GPIO_G, (1<<7),        13, (1<<6)},
+#endif
 	[IT83XX_IRQ_WKO128] =   {GPIO_J, (1<<0),        14, (1<<0)},
 	[IT83XX_IRQ_WKO129] =   {GPIO_J, (1<<1),        14, (1<<1)},
 	[IT83XX_IRQ_WKO130] =   {GPIO_J, (1<<2),        14, (1<<2)},
@@ -165,6 +197,15 @@ static const struct {
 	[IT83XX_IRQ_WKO141] =   {GPIO_L, (1<<5),        15, (1<<5)},
 	[IT83XX_IRQ_WKO142] =   {GPIO_L, (1<<6),        15, (1<<6)},
 	[IT83XX_IRQ_WKO143] =   {GPIO_L, (1<<7),        15, (1<<7)},
+#ifdef IT83XX_GPIO_INT_FLEXIBLE
+	[IT83XX_IRQ_WKO144] =   {GPIO_M, (1<<0),        16, (1<<0)},
+	[IT83XX_IRQ_WKO145] =   {GPIO_M, (1<<1),        16, (1<<1)},
+	[IT83XX_IRQ_WKO146] =   {GPIO_M, (1<<2),        16, (1<<2)},
+	[IT83XX_IRQ_WKO147] =   {GPIO_M, (1<<3),        16, (1<<3)},
+	[IT83XX_IRQ_WKO148] =   {GPIO_M, (1<<4),        16, (1<<4)},
+	[IT83XX_IRQ_WKO149] =   {GPIO_M, (1<<5),        16, (1<<5)},
+	[IT83XX_IRQ_WKO150] =   {GPIO_M, (1<<6),        16, (1<<6)},
+#endif
 	[IT83XX_IRQ_COUNT-1] =  {0,           0,         0,      0},
 };
 BUILD_ASSERT(ARRAY_SIZE(gpio_irqs) == IT83XX_IRQ_COUNT);
@@ -196,6 +237,86 @@ struct gpio_1p8v_t {
 };
 
 static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = {
+#ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED
+	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, (1 << 0)},
+		     [5] = {&IT83XX_GPIO_GRC24, (1 << 1)},
+		     [6] = {&IT83XX_GPIO_GRC24, (1 << 5)},
+		     [7] = {&IT83XX_GPIO_GRC24, (1 << 6)} },
+	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, (1 << 1)},
+		     [4] = {&IT83XX_GPIO_GRC22, (1 << 0)},
+		     [5] = {&IT83XX_GPIO_GRC19, (1 << 7)},
+		     [6] = {&IT83XX_GPIO_GRC19, (1 << 6)},
+		     [7] = {&IT83XX_GPIO_GRC24, (1 << 4)} },
+	[GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, (1 << 7)},
+		     [1] = {&IT83XX_GPIO_GRC19, (1 << 5)},
+		     [2] = {&IT83XX_GPIO_GRC19, (1 << 4)},
+		     [4] = {&IT83XX_GPIO_GRC24, (1 << 2)},
+		     [6] = {&IT83XX_GPIO_GRC24, (1 << 3)},
+		     [7] = {&IT83XX_GPIO_GRC19, (1 << 3)} },
+	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, (1 << 2)},
+		     [1] = {&IT83XX_GPIO_GRC19, (1 << 1)},
+		     [2] = {&IT83XX_GPIO_GRC19, (1 << 0)},
+		     [3] = {&IT83XX_GPIO_GRC20, (1 << 7)},
+		     [4] = {&IT83XX_GPIO_GRC20, (1 << 6)},
+		     [5] = {&IT83XX_GPIO_GRC22, (1 << 4)},
+		     [6] = {&IT83XX_GPIO_GRC22, (1 << 5)},
+		     [7] = {&IT83XX_GPIO_GRC22, (1 << 6)} },
+	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, (1 << 5)},
+		     [1] = {&IT83XX_GPIO_GCR28, (1 << 6)},
+		     [2] = {&IT83XX_GPIO_GCR28, (1 << 7)},
+		     [4] = {&IT83XX_GPIO_GRC22, (1 << 2)},
+		     [5] = {&IT83XX_GPIO_GRC22, (1 << 3)},
+		     [6] = {&IT83XX_GPIO_GRC20, (1 << 4)},
+		     [7] = {&IT83XX_GPIO_GRC20, (1 << 3)} },
+	[GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, (1 << 4)},
+		     [1] = {&IT83XX_GPIO_GCR28, (1 << 5)},
+		     [2] = {&IT83XX_GPIO_GRC20, (1 << 2)},
+		     [3] = {&IT83XX_GPIO_GRC20, (1 << 1)},
+		     [4] = {&IT83XX_GPIO_GRC20, (1 << 0)},
+		     [5] = {&IT83XX_GPIO_GRC21, (1 << 7)},
+		     [6] = {&IT83XX_GPIO_GRC21, (1 << 6)},
+		     [7] = {&IT83XX_GPIO_GRC21, (1 << 5)} },
+	[GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, (1 << 2)},
+		     [1] = {&IT83XX_GPIO_GRC21, (1 << 4)},
+		     [2] = {&IT83XX_GPIO_GCR28, (1 << 3)},
+		     [6] = {&IT83XX_GPIO_GRC21, (1 << 3)} },
+	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, (1 << 2)},
+		     [1] = {&IT83XX_GPIO_GRC21, (1 << 1)},
+		     [2] = {&IT83XX_GPIO_GRC21, (1 << 0)},
+		     [5] = {&IT83XX_GPIO_GCR27, (1 << 7)},
+		     [6] = {&IT83XX_GPIO_GCR28, (1 << 0)} },
+	[GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, (1 << 3)},
+		     [1] = {&IT83XX_GPIO_GRC23, (1 << 4)},
+		     [2] = {&IT83XX_GPIO_GRC23, (1 << 5)},
+		     [3] = {&IT83XX_GPIO_GRC23, (1 << 6)},
+		     [4] = {&IT83XX_GPIO_GRC23, (1 << 7)},
+		     [5] = {&IT83XX_GPIO_GCR27, (1 << 4)},
+		     [6] = {&IT83XX_GPIO_GCR27, (1 << 5)},
+		     [7] = {&IT83XX_GPIO_GCR27, (1 << 6)} },
+	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, (1 << 0)},
+		     [1] = {&IT83XX_GPIO_GRC23, (1 << 1)},
+		     [2] = {&IT83XX_GPIO_GRC23, (1 << 2)},
+		     [3] = {&IT83XX_GPIO_GRC23, (1 << 3)},
+		     [4] = {&IT83XX_GPIO_GCR27, (1 << 0)},
+		     [5] = {&IT83XX_GPIO_GCR27, (1 << 1)},
+		     [6] = {&IT83XX_GPIO_GCR27, (1 << 2)} },
+	[GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, (1 << 0)},
+		     [1] = {&IT83XX_GPIO_GCR26, (1 << 1)},
+		     [2] = {&IT83XX_GPIO_GCR26, (1 << 2)},
+		     [3] = {&IT83XX_GPIO_GCR26, (1 << 3)},
+		     [4] = {&IT83XX_GPIO_GCR26, (1 << 4)},
+		     [5] = {&IT83XX_GPIO_GCR26, (1 << 5)},
+		     [6] = {&IT83XX_GPIO_GCR26, (1 << 6)},
+		     [7] = {&IT83XX_GPIO_GCR26, (1 << 7)} },
+	[GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, (1 << 0)},
+		     [1] = {&IT83XX_GPIO_GCR25, (1 << 1)},
+		     [2] = {&IT83XX_GPIO_GCR25, (1 << 2)},
+		     [3] = {&IT83XX_GPIO_GCR25, (1 << 3)},
+		     [4] = {&IT83XX_GPIO_GCR25, (1 << 4)},
+		     [5] = {&IT83XX_GPIO_GCR25, (1 << 5)},
+		     [6] = {&IT83XX_GPIO_GCR25, (1 << 6)},
+		     [7] = {&IT83XX_GPIO_GCR25, (1 << 7)} },
+#else
 	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, (1 << 0)},
 		     [5] = {&IT83XX_GPIO_GRC24, (1 << 1)} },
 	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, (1 << 1)},
@@ -230,14 +351,21 @@ static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = {
 		     [1] = {&IT83XX_GPIO_GRC23, (1 << 1)},
 		     [2] = {&IT83XX_GPIO_GRC23, (1 << 2)},
 		     [3] = {&IT83XX_GPIO_GRC23, (1 << 3)} },
+#endif
 };
 
 static void gpio_1p8v_3p3v_sel_by_pin(uint8_t port, uint8_t pin, int sel_1p8v)
 {
+	volatile uint8_t *reg_1p8v = gpio_1p8v_sel[port][pin].reg;
+	uint8_t sel = gpio_1p8v_sel[port][pin].sel;
+
+	if (reg_1p8v == NULL)
+		return;
+
 	if (sel_1p8v)
-		*gpio_1p8v_sel[port][pin].reg |= gpio_1p8v_sel[port][pin].sel;
+		*reg_1p8v |= sel;
 	else
-		*gpio_1p8v_sel[port][pin].reg &= ~gpio_1p8v_sel[port][pin].sel;
+		*reg_1p8v &= ~sel;
 }
 
 void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func)
@@ -293,6 +421,7 @@ void gpio_kbs_pin_gpio_mode(uint32_t port, uint32_t mask, uint32_t flags)
 		IT83XX_KBS_KSIGCTRL |= mask;
 }
 
+#ifndef IT83XX_GPIO_INT_FLEXIBLE
 /* Returns true when the falling trigger bit actually mean both trigger. */
 static int group_falling_is_both(const int group)
 {
@@ -315,6 +444,7 @@ static const char *get_gpio_string(const int port, const int mask)
 	}
 	return buffer;
 }
+#endif /* IT83XX_GPIO_INT_FLEXIBLE */
 
 void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 {
@@ -380,16 +510,36 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 		wuc_group = gpio_irqs[irq].wuc_group;
 		wuc_mask = gpio_irqs[irq].wuc_mask;
 
+		/*
+		 * Set both edges interrupt.
+		 * The WUBEMR register is valid on IT8320 DX version.
+		 * And the setting (falling or rising edge) of WUEMR register is
+		 * invalid if this mode is set.
+		 */
+#ifdef IT83XX_GPIO_INT_FLEXIBLE
+		if ((flags & GPIO_INT_BOTH) == GPIO_INT_BOTH)
+			*(wubemr(wuc_group)) |= wuc_mask;
+		else
+			*(wubemr(wuc_group)) &= ~wuc_mask;
+#endif
+
 		if (flags & GPIO_INT_F_FALLING) {
+#ifndef IT83XX_GPIO_INT_FLEXIBLE
 			if (!!(flags & GPIO_INT_F_RISING) !=
 			    group_falling_is_both(wuc_group)) {
 				ccprintf("!!Fix GPIO %s interrupt config!!\n",
 					 get_gpio_string(port, mask));
 			}
+#endif
 			*(wuemr(wuc_group)) |= wuc_mask;
 		} else {
 			*(wuemr(wuc_group)) &= ~wuc_mask;
 		}
+		/*
+		 * Always write 1 to clear the WUC status register after
+		 * modifying edge mode selection register (WUBEMR and WUEMR).
+		 */
+		*(wuesr(wuc_group)) = wuc_mask;
 	}
 }
 
diff --git a/chip/it83xx/irq.c b/chip/it83xx/irq.c
index 44f826bba5..fb2c0ee167 100644
--- a/chip/it83xx/irq.c
+++ b/chip/it83xx/irq.c
@@ -19,7 +19,7 @@ static const struct {
 	uint8_t isr_off;
 	uint8_t ier_off;
 	uint8_t cpu_int[8];
-} irq_groups[21] = {
+} irq_groups[23] = {
 	IRQ_GROUP(0,  {-1,  2,  5,  4,  6,  2,  2,  4}),
 	IRQ_GROUP(1,  { 7,  6,  6,  5,  2,  2,  2,  8}),
 	IRQ_GROUP(2,  { 6,  2,  8,  8,  8,  2, 12, 12}),
@@ -38,9 +38,16 @@ static const struct {
 	IRQ_GROUP(15, { 2,  2,  2,  2,  2,  2,  2,  2}),
 	IRQ_GROUP(16, { 2,  2,  2,  2,  2,  2,  2, -1}),
 	IRQ_GROUP(17, { 2,  2,  2,  2,  2,  2,  2,  2}),
-	IRQ_GROUP(18, {-1, -1, -1, -1, -1,  4,  4,  7}),
+	IRQ_GROUP(18, { 2,  2,  2,  2, -1,  4,  4,  7}),
 	IRQ_GROUP(19, { 6,  6, 12,  3,  3,  3,  3,  3}),
-	IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, 12}),
+	IRQ_GROUP(20, {12, 12, 12, 12, 12, 12, 12, -1}),
+#ifdef IT83XX_INTC_GROUP_21_22_SUPPORT
+	IRQ_GROUP(21, { 2,  2,  2,  2,  2,  2,  2,  2}),
+	IRQ_GROUP(22, { 2,  2, -1, -1, -1, -1, -1, -1}),
+#else
+	IRQ_GROUP(21, {-1, -1, -1, -1, -1, -1, -1, -1}),
+	IRQ_GROUP(22, {-1, -1, -1, -1, -1, -1, -1, -1}),
+#endif
 };
 
 int chip_enable_irq(int irq)
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index 3536208226..a62753c9b1 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -172,6 +172,10 @@
 #define IT83XX_IRQ_WKO142         142
 #define IT83XX_IRQ_WKO143         143
 /* Group 18 */
+#define IT83XX_IRQ_WKO123         144
+#define IT83XX_IRQ_WKO124         145
+#define IT83XX_IRQ_WKO125         146
+#define IT83XX_IRQ_WKO126         147
 #define IT83XX_IRQ_PMC5_OUT       149
 #define IT83XX_IRQ_PMC5_IN        150
 #define IT83XX_IRQ_V_COMP         151
@@ -192,9 +196,20 @@
 #define IT83XX_IRQ_PCH_P80        164
 #define IT83XX_IRQ_USBPD0         165
 #define IT83XX_IRQ_USBPD1         166
-#define IT83XX_IRQ_ESPI_SLAVE     167
-
-#define IT83XX_IRQ_COUNT          168
+/* Group 21 */
+#define IT83XX_IRQ_WKO40          168
+#define IT83XX_IRQ_WKO45          169
+#define IT83XX_IRQ_WKO46          170
+#define IT83XX_IRQ_WKO144         171
+#define IT83XX_IRQ_WKO145         172
+#define IT83XX_IRQ_WKO146         173
+#define IT83XX_IRQ_WKO147         174
+#define IT83XX_IRQ_WKO148         175
+/* Group 22 */
+#define IT83XX_IRQ_WKO149         176
+#define IT83XX_IRQ_WKO150         177
+
+#define IT83XX_IRQ_COUNT          178
 
 /* IRQ dispatching to CPU INT vectors */
 #define IT83XX_CPU_INT_IRQ_1       2
@@ -337,6 +352,10 @@
 #define IT83XX_CPU_INT_IRQ_141     2
 #define IT83XX_CPU_INT_IRQ_142     2
 #define IT83XX_CPU_INT_IRQ_143     2
+#define IT83XX_CPU_INT_IRQ_144     2
+#define IT83XX_CPU_INT_IRQ_145     2
+#define IT83XX_CPU_INT_IRQ_146     2
+#define IT83XX_CPU_INT_IRQ_147     2
 #define IT83XX_CPU_INT_IRQ_149     4
 #define IT83XX_CPU_INT_IRQ_150     4
 #define IT83XX_CPU_INT_IRQ_151     7
@@ -356,6 +375,16 @@
 #define IT83XX_CPU_INT_IRQ_165    12
 #define IT83XX_CPU_INT_IRQ_166    12
 #define IT83XX_CPU_INT_IRQ_167    12
+#define IT83XX_CPU_INT_IRQ_168     2
+#define IT83XX_CPU_INT_IRQ_169     2
+#define IT83XX_CPU_INT_IRQ_170     2
+#define IT83XX_CPU_INT_IRQ_171     2
+#define IT83XX_CPU_INT_IRQ_172     2
+#define IT83XX_CPU_INT_IRQ_173     2
+#define IT83XX_CPU_INT_IRQ_174     2
+#define IT83XX_CPU_INT_IRQ_175     2
+#define IT83XX_CPU_INT_IRQ_176     2
+#define IT83XX_CPU_INT_IRQ_177     2
 
 /* "Fake" IRQ to declare in readable fashion all WKO IRQ routed to INT#2 */
 #define CPU_INT_2_ALL_GPIOS      255
@@ -412,6 +441,8 @@
 #define IT83XX_INTC_IER18   REG8(IT83XX_INTC_BASE+0x4d)
 #define IT83XX_INTC_IER19   REG8(IT83XX_INTC_BASE+0x51)
 #define IT83XX_INTC_IER20   REG8(IT83XX_INTC_BASE+0x55)
+#define IT83XX_INTC_IER21   REG8(IT83XX_INTC_BASE+0x59)
+#define IT83XX_INTC_IER22   REG8(IT83XX_INTC_BASE+0x5d)
 
 #define IT83XX_INTC_ISR0    REG8(IT83XX_INTC_BASE+0x00)
 #define IT83XX_INTC_ISR1    REG8(IT83XX_INTC_BASE+0x01)
@@ -434,53 +465,16 @@
 #define IT83XX_INTC_ISR18   REG8(IT83XX_INTC_BASE+0x4c)
 #define IT83XX_INTC_ISR19   REG8(IT83XX_INTC_BASE+0x50)
 #define IT83XX_INTC_ISR20   REG8(IT83XX_INTC_BASE+0x54)
+#define IT83XX_INTC_ISR21   REG8(IT83XX_INTC_BASE+0x58)
+#define IT83XX_INTC_ISR22   REG8(IT83XX_INTC_BASE+0x5c)
 
 #define IT83XX_INTC_IELMR10 REG8(IT83XX_INTC_BASE+0x2E)
 #define IT83XX_INTC_IPOLR10 REG8(IT83XX_INTC_BASE+0x2F)
 #define IT83XX_INTC_IELMR19 REG8(IT83XX_INTC_BASE+0x52)
 #define IT83XX_INTC_IPOLR19 REG8(IT83XX_INTC_BASE+0x53)
 
-#define IT83XX_INTC_EXT_IER0    REG8(IT83XX_INTC_BASE+0x60)
-#define IT83XX_INTC_EXT_IER1    REG8(IT83XX_INTC_BASE+0x61)
-#define IT83XX_INTC_EXT_IER2    REG8(IT83XX_INTC_BASE+0x62)
-#define IT83XX_INTC_EXT_IER3    REG8(IT83XX_INTC_BASE+0x63)
-#define IT83XX_INTC_EXT_IER4    REG8(IT83XX_INTC_BASE+0x64)
-#define IT83XX_INTC_EXT_IER5    REG8(IT83XX_INTC_BASE+0x65)
-#define IT83XX_INTC_EXT_IER6    REG8(IT83XX_INTC_BASE+0x66)
-#define IT83XX_INTC_EXT_IER7    REG8(IT83XX_INTC_BASE+0x67)
-#define IT83XX_INTC_EXT_IER8    REG8(IT83XX_INTC_BASE+0x68)
-#define IT83XX_INTC_EXT_IER9    REG8(IT83XX_INTC_BASE+0x69)
-#define IT83XX_INTC_EXT_IER10   REG8(IT83XX_INTC_BASE+0x6A)
-#define IT83XX_INTC_EXT_IER11   REG8(IT83XX_INTC_BASE+0x6B)
-#define IT83XX_INTC_EXT_IER12   REG8(IT83XX_INTC_BASE+0x6C)
-#define IT83XX_INTC_EXT_IER13   REG8(IT83XX_INTC_BASE+0x6D)
-#define IT83XX_INTC_EXT_IER14   REG8(IT83XX_INTC_BASE+0x6E)
-#define IT83XX_INTC_EXT_IER15   REG8(IT83XX_INTC_BASE+0x6F)
-#define IT83XX_INTC_EXT_IER16   REG8(IT83XX_INTC_BASE+0x70)
-#define IT83XX_INTC_EXT_IER17   REG8(IT83XX_INTC_BASE+0x71)
-#define IT83XX_INTC_EXT_IER18   REG8(IT83XX_INTC_BASE+0x72)
-#define IT83XX_INTC_EXT_IER19   REG8(IT83XX_INTC_BASE+0x73)
-#define IT83XX_INTC_EXT_IER20   REG8(IT83XX_INTC_BASE+0x74)
-
 #define IT83XX_INTC_EXT_IER_OFF(n) (0x60 + (n))
-
 #define IT83XX_INTC_IVCT(i)     REG8(IT83XX_INTC_BASE+0x80+(i))
-#define IT83XX_INTC_IVCT0       REG8(IT83XX_INTC_BASE+0x80)
-#define IT83XX_INTC_IVCT1       REG8(IT83XX_INTC_BASE+0x81)
-#define IT83XX_INTC_IVCT2       REG8(IT83XX_INTC_BASE+0x82)
-#define IT83XX_INTC_IVCT3       REG8(IT83XX_INTC_BASE+0x83)
-#define IT83XX_INTC_IVCT4       REG8(IT83XX_INTC_BASE+0x84)
-#define IT83XX_INTC_IVCT5       REG8(IT83XX_INTC_BASE+0x85)
-#define IT83XX_INTC_IVCT6       REG8(IT83XX_INTC_BASE+0x86)
-#define IT83XX_INTC_IVCT7       REG8(IT83XX_INTC_BASE+0x87)
-#define IT83XX_INTC_IVCT8       REG8(IT83XX_INTC_BASE+0x88)
-#define IT83XX_INTC_IVCT9       REG8(IT83XX_INTC_BASE+0x89)
-#define IT83XX_INTC_IVCT10      REG8(IT83XX_INTC_BASE+0x8A)
-#define IT83XX_INTC_IVCT11      REG8(IT83XX_INTC_BASE+0x8B)
-#define IT83XX_INTC_IVCT12      REG8(IT83XX_INTC_BASE+0x8C)
-#define IT83XX_INTC_IVCT13      REG8(IT83XX_INTC_BASE+0x8D)
-#define IT83XX_INTC_IVCT14      REG8(IT83XX_INTC_BASE+0x8E)
-#define IT83XX_INTC_IVCT15      REG8(IT83XX_INTC_BASE+0x8F)
 
 /* --- EC Access to the Host Controlled Modules (EC2I Bridge) --- */
 #define IT83XX_EC2I_BASE  0x00F01200
@@ -503,6 +497,8 @@
 #define IT83XX_WUC_WUEMR5 (IT83XX_WUC_BASE+0x0c)
 #define IT83XX_WUC_WUESR1 (IT83XX_WUC_BASE+0x04)
 #define IT83XX_WUC_WUESR5 (IT83XX_WUC_BASE+0x0d)
+#define IT83XX_WUC_WUBEMR1 (IT83XX_WUC_BASE+0x3c)
+#define IT83XX_WUC_WUBEMR5 (IT83XX_WUC_BASE+0x0f)
 
 #define IT83XX_WUC_WUESR10    REG8(IT83XX_WUC_BASE+0x21)
 #define IT83XX_WUC_WUESR11    REG8(IT83XX_WUC_BASE+0x25)
@@ -641,6 +637,10 @@
 #define IT83XX_GPIO_GRC22       REG8(IT83XX_GPIO_BASE+0xE7)
 #define IT83XX_GPIO_GRC23       REG8(IT83XX_GPIO_BASE+0xE8)
 #define IT83XX_GPIO_GRC24       REG8(IT83XX_GPIO_BASE+0xE9)
+#define IT83XX_GPIO_GCR25       REG8(IT83XX_GPIO_BASE+0xD1)
+#define IT83XX_GPIO_GCR26       REG8(IT83XX_GPIO_BASE+0xD2)
+#define IT83XX_GPIO_GCR27       REG8(IT83XX_GPIO_BASE+0xD3)
+#define IT83XX_GPIO_GCR28       REG8(IT83XX_GPIO_BASE+0xD4)
 
 #define IT83XX_GPIO_DATA_BASE        (IT83XX_GPIO_BASE + 0x00)
 #define IT83XX_GPIO_OUTPUT_TYPE_BASE (IT83XX_GPIO_BASE + 0x70)
@@ -779,6 +779,7 @@ enum clock_gate_offsets {
 #define IT83XX_GCTRL_IVTBAR       REG8(IT83XX_GCTRL_BASE+0x41)
 #define IT83XX_GCTRL_MCCR2        REG8(IT83XX_GCTRL_BASE+0x44)
 #define IT83XX_GCTRL_SSCR         REG8(IT83XX_GCTRL_BASE+0x4A)
+#define IT83XX_GCTRL_ETWDUARTCR   REG8(IT83XX_GCTRL_BASE+0x4B)
 #define IT83XX_GCTRL_EWPR0PFH(i)  REG8(IT83XX_GCTRL_BASE+0x60+i)
 #define IT83XX_GCTRL_EWPR0PFD(i)  REG8(IT83XX_GCTRL_BASE+0xA0+i)
 #define IT83XX_GCTRL_EWPR0PFEC(i) REG8(IT83XX_GCTRL_BASE+0xC0+i)
@@ -1227,6 +1228,7 @@ enum usbpd_port {
 
 #define IT83XX_ESPI_BASE  0x00F03100
 
+#define IT83XX_ESPI_GCAC1      REG8(IT83XX_ESPI_BASE+0x05)
 #define IT83XX_ESPI_ESPCTRL0   REG8(IT83XX_ESPI_BASE+0x90)
 #define IT83XX_ESPI_ESGCTRL0   REG8(IT83XX_ESPI_BASE+0xA0)
 #define IT83XX_ESPI_ESGCTRL1   REG8(IT83XX_ESPI_BASE+0xA1)
diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c
index 23e832b902..6a2c80cf84 100644
--- a/chip/it83xx/system.c
+++ b/chip/it83xx/system.c
@@ -165,9 +165,14 @@ void system_reset(int flags)
 	 */
 	IT83XX_SMB_SLVISELR |= (1 << 4);
 
+	/* bit0: enable watchdog hardware reset. */
+#ifdef IT83XX_ETWD_HW_RESET_SUPPORT
+	if (flags & SYSTEM_RESET_HARD)
+		IT83XX_GCTRL_ETWDUARTCR |= (1 << 0);
+#endif
 	/*
-	 * Writing invalid key to watchdog module triggers a soft reset. For
-	 * now this is the only option, no hard reset.
+	 * Writing invalid key to watchdog module triggers a soft or hardware
+	 * reset. It depends on the setting of bit0 at ETWDUARTCR register.
 	 */
 	IT83XX_ETWD_ETWCFG |= 0x20;
 	IT83XX_ETWD_EWDKEYR = 0x00;