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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-05-11 10:16:41 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-12 20:54:37 +0000 |
| commit | 39bd18b890bb708e79e9ba50dd3b5bf3d35e9ff1 (patch) | |
| tree | 69b9331013e942bcbae05c10f863ad0ae9bc4f3b /chip/it83xx | |
| parent | 3a36c29e6756231f2fb1fdd26447d519cbd5b26a (diff) | |
| download | chrome-ec-39bd18b890bb708e79e9ba50dd3b5bf3d35e9ff1.tar.gz | |
cleanup: Rename image geometry CONFIGs
Rename image geometry configs with a uniform naming scheme to make their
purposes more clear.
CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory
CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage
CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image
CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory
CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage
CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image
CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage
CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage
BUG=chrome-os-partner:39741,chrome-os-partner:23796
TEST=Set date / version strings to constants then `make buildall -j`.
Verify that each ec.bin image is identical pre- and post-change.
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd
Reviewed-on: https://chromium-review.googlesource.com/270189
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Diffstat (limited to 'chip/it83xx')
| -rw-r--r-- | chip/it83xx/config_chip.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/chip/it83xx/config_chip.h b/chip/it83xx/config_chip.h index d7b13d1480..5caf50562b 100644 --- a/chip/it83xx/config_chip.h +++ b/chip/it83xx/config_chip.h @@ -62,7 +62,7 @@ #endif /* RO firmware must start at beginning of flash */ -#define CONFIG_FW_RO_OFF 0 +#define CONFIG_RO_MEM_OFF 0 /* * The EC uses the one bank of flash to emulate a SPI-like write protect @@ -71,18 +71,18 @@ #define CONFIG_FW_PSTATE_SIZE CONFIG_FLASH_BANK_SIZE /* PSTATE immediately follows RO, in the first half of flash */ -#define CONFIG_FW_RO_SIZE (CONFIG_FW_IMAGE_SIZE \ +#define CONFIG_RO_SIZE (CONFIG_FW_IMAGE_SIZE \ - CONFIG_FW_PSTATE_SIZE) -#define CONFIG_FW_PSTATE_OFF CONFIG_FW_RO_SIZE +#define CONFIG_FW_PSTATE_OFF CONFIG_RO_SIZE #define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE /* RW firmware is one firmware image offset from the start */ -#define CONFIG_FW_RW_OFF CONFIG_FW_IMAGE_SIZE -#define CONFIG_FW_RW_SIZE CONFIG_FW_IMAGE_SIZE +#define CONFIG_RW_MEM_OFF CONFIG_FW_IMAGE_SIZE +#define CONFIG_RW_SIZE CONFIG_FW_IMAGE_SIZE /* TODO: why 2 sets of configs with the same numbers? */ -#define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF -#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE +#define CONFIG_WP_OFF CONFIG_RO_MEM_OFF +#define CONFIG_WP_SIZE CONFIG_RO_SIZE /****************************************************************************/ /* Customize the build */ |