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authorDino Li <dino.li@ite.com.tw>2015-06-29 17:48:54 +0800
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>2015-06-30 17:18:54 +0000
commite881d99fde5bc818b72bea91ce8cd1daa70bc760 (patch)
tree47a3c44e7c40e01e0150e1af0eaf295932eab569 /chip/it83xx
parent362174b49b50fcd5d8a2542662e576b7e69321a1 (diff)
downloadchrome-ec-e881d99fde5bc818b72bea91ce8cd1daa70bc760.tar.gz
it8380dev: add pin 3.3v/1.8v selection
add GPIO_SEL_1P8V flag for 1.8v/3.3v selection. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. To configure 1.8V/3.3V pin to 1.8V, set GPIO_SEL_1P8V flag in gpio.inc. 2. The corresponding bit will be set as default value if the pin is not listed in gpio.inc. Change-Id: Ica02aabe40b83fcb4d33bd28d717a0633bdef5f3 Reviewed-on: https://chromium-review.googlesource.com/281842 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
Diffstat (limited to 'chip/it83xx')
-rw-r--r--chip/it83xx/gpio.c75
-rw-r--r--chip/it83xx/registers.h6
-rw-r--r--chip/it83xx/system.c21
3 files changed, 100 insertions, 2 deletions
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
index 24ef6ac78d..7ad348ce4b 100644
--- a/chip/it83xx/gpio.c
+++ b/chip/it83xx/gpio.c
@@ -9,12 +9,13 @@
#include "common.h"
#include "gpio.h"
#include "hooks.h"
+#include "kmsc_chip.h"
#include "registers.h"
#include "switch.h"
+#include "system.h"
#include "task.h"
#include "timer.h"
#include "util.h"
-#include "kmsc_chip.h"
/*
* Converts port (ie GPIO A) to base address offset of the control register
@@ -174,6 +175,67 @@ static int gpio_to_irq(uint8_t port, uint8_t mask)
return -1;
}
+struct gpio_1p8v_t {
+ uint8_t gpio_port;
+ uint8_t gpio_mask;
+ volatile uint8_t *ctrl_reg;
+ uint8_t ctrl_mask;
+};
+
+const struct gpio_1p8v_t gpio_1p8v_ctrl[] = {
+ {GPIO_A, (1 << 4), &IT83XX_GPIO_GRC24, (1 << 0)},
+ {GPIO_A, (1 << 5), &IT83XX_GPIO_GRC24, (1 << 1)},
+ {GPIO_B, (1 << 3), &IT83XX_GPIO_GRC22, (1 << 1)},
+ {GPIO_B, (1 << 4), &IT83XX_GPIO_GRC22, (1 << 0)},
+ {GPIO_B, (1 << 5), &IT83XX_GPIO_GRC19, (1 << 7)},
+ {GPIO_B, (1 << 6), &IT83XX_GPIO_GRC19, (1 << 6)},
+ {GPIO_C, (1 << 1), &IT83XX_GPIO_GRC19, (1 << 5)},
+ {GPIO_C, (1 << 2), &IT83XX_GPIO_GRC19, (1 << 4)},
+ {GPIO_C, (1 << 7), &IT83XX_GPIO_GRC19, (1 << 3)},
+ {GPIO_D, (1 << 0), &IT83XX_GPIO_GRC19, (1 << 2)},
+ {GPIO_D, (1 << 1), &IT83XX_GPIO_GRC19, (1 << 1)},
+ {GPIO_D, (1 << 2), &IT83XX_GPIO_GRC19, (1 << 0)},
+ {GPIO_D, (1 << 3), &IT83XX_GPIO_GRC20, (1 << 7)},
+ {GPIO_D, (1 << 4), &IT83XX_GPIO_GRC20, (1 << 6)},
+ {GPIO_E, (1 << 0), &IT83XX_GPIO_GRC20, (1 << 5)},
+ {GPIO_E, (1 << 6), &IT83XX_GPIO_GRC20, (1 << 4)},
+ {GPIO_E, (1 << 7), &IT83XX_GPIO_GRC20, (1 << 3)},
+ {GPIO_F, (1 << 2), &IT83XX_GPIO_GRC20, (1 << 2)},
+ {GPIO_F, (1 << 3), &IT83XX_GPIO_GRC20, (1 << 1)},
+ {GPIO_F, (1 << 4), &IT83XX_GPIO_GRC20, (1 << 0)},
+ {GPIO_F, (1 << 5), &IT83XX_GPIO_GRC21, (1 << 7)},
+ {GPIO_F, (1 << 6), &IT83XX_GPIO_GRC21, (1 << 6)},
+ {GPIO_F, (1 << 7), &IT83XX_GPIO_GRC21, (1 << 5)},
+ {GPIO_H, (1 << 0), &IT83XX_GPIO_GRC21, (1 << 2)},
+ {GPIO_H, (1 << 1), &IT83XX_GPIO_GRC21, (1 << 1)},
+ {GPIO_H, (1 << 2), &IT83XX_GPIO_GRC21, (1 << 0)},
+ {GPIO_I, (1 << 1), &IT83XX_GPIO_GRC23, (1 << 4)},
+ {GPIO_I, (1 << 2), &IT83XX_GPIO_GRC23, (1 << 5)},
+ {GPIO_I, (1 << 3), &IT83XX_GPIO_GRC23, (1 << 6)},
+ {GPIO_I, (1 << 4), &IT83XX_GPIO_GRC23, (1 << 7)},
+ {GPIO_J, (1 << 0), &IT83XX_GPIO_GRC23, (1 << 0)},
+ {GPIO_J, (1 << 1), &IT83XX_GPIO_GRC23, (1 << 1)},
+ {GPIO_J, (1 << 2), &IT83XX_GPIO_GRC23, (1 << 2)},
+ {GPIO_J, (1 << 3), &IT83XX_GPIO_GRC23, (1 << 3)},
+};
+
+static void gpio_1p8v_3p3v_sel(uint8_t port, uint8_t mask, uint32_t flags)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gpio_1p8v_ctrl); i++) {
+ if (gpio_1p8v_ctrl[i].gpio_port == port &&
+ gpio_1p8v_ctrl[i].gpio_mask == mask) {
+ if (flags & GPIO_SEL_1P8V)
+ *gpio_1p8v_ctrl[i].ctrl_reg |=
+ gpio_1p8v_ctrl[i].ctrl_mask;
+ else
+ *gpio_1p8v_ctrl[i].ctrl_reg &=
+ ~gpio_1p8v_ctrl[i].ctrl_mask;
+ break;
+ }
+ }
+}
void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func)
{
@@ -227,6 +289,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
else
IT83XX_GPIO_GPOT(port) &= ~mask;
+ /* To select 1.8v or 3.3v support. */
+ gpio_1p8v_3p3v_sel(port, mask, flags);
+
/* If output, set level before changing type to an output. */
if (flags & GPIO_OUTPUT) {
if (flags & GPIO_HIGH)
@@ -316,6 +381,7 @@ int gpio_disable_interrupt(enum gpio_signal signal)
void gpio_pre_init(void)
{
const struct gpio_info *g = gpio_list;
+ int is_warm = gpio_is_reboot_warm();
int flags;
int i;
@@ -325,6 +391,13 @@ void gpio_pre_init(void)
if (flags & GPIO_DEFAULT)
continue;
+ /*
+ * If this is a warm reboot, don't set the output levels or
+ * we'll shut off the AP.
+ */
+ if (is_warm)
+ flags &= ~(GPIO_LOW | GPIO_HIGH);
+
/* Set up GPIO based on flags */
gpio_set_flags_by_mask(g->port, g->mask, flags);
}
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index 47113ecd12..c918d3eb5b 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -531,6 +531,12 @@
#define IT83XX_GPIO_GRC6 REG8(IT83XX_GPIO_BASE+0xF5)
#define IT83XX_GPIO_GRC7 REG8(IT83XX_GPIO_BASE+0xF6)
#define IT83XX_GPIO_GRC8 REG8(IT83XX_GPIO_BASE+0xF7)
+#define IT83XX_GPIO_GRC19 REG8(IT83XX_GPIO_BASE+0xE4)
+#define IT83XX_GPIO_GRC20 REG8(IT83XX_GPIO_BASE+0xE5)
+#define IT83XX_GPIO_GRC21 REG8(IT83XX_GPIO_BASE+0xE6)
+#define IT83XX_GPIO_GRC22 REG8(IT83XX_GPIO_BASE+0xE7)
+#define IT83XX_GPIO_GRC23 REG8(IT83XX_GPIO_BASE+0xE8)
+#define IT83XX_GPIO_GRC24 REG8(IT83XX_GPIO_BASE+0xE9)
#define IT83XX_GPIO_DATA_BASE (IT83XX_GPIO_BASE + 0x00)
#define IT83XX_GPIO_OUTPUT_TYPE_BASE (IT83XX_GPIO_BASE + 0x70)
diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c
index e5110c83e1..ffeae356fe 100644
--- a/chip/it83xx/system.c
+++ b/chip/it83xx/system.c
@@ -55,11 +55,30 @@ static void check_reset_cause(void)
system_set_reset_flags(flags);
}
+int gpio_is_reboot_warm(void)
+{
+ uint32_t reset_flags;
+ /*
+ * Check reset cause here,
+ * gpio_pre_init is executed faster than system_pre_init
+ */
+ check_reset_cause();
+ reset_flags = system_get_reset_flags();
+
+ if ((reset_flags & RESET_FLAG_RESET_PIN) ||
+ (reset_flags & RESET_FLAG_POWER_ON) ||
+ (reset_flags & RESET_FLAG_WATCHDOG) ||
+ (reset_flags & RESET_FLAG_HARD) ||
+ (reset_flags & RESET_FLAG_SOFT))
+ return 0;
+ else
+ return 1;
+}
+
void system_pre_init(void)
{
/* TODO(crosbug.com/p/23575): IMPLEMENT ME ! */
- check_reset_cause();
}
void system_reset(int flags)