common: replace 1 << digits, with BIT(digits)

Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.

Fix an error in motion_lid try to set bit 31 of a signed integer.

BUG=None
BRANCH=None
TEST=compile

Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>

13 files changed, 338 insertions, 338 deletions

diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c
index 6b8361dbdb..71f92c44e9 100644
--- a/chip/it83xx/adc.c
+++ b/chip/it83xx/adc.c
@@ -222,8 +222,8 @@ static void adc_init(void)
 	 * NOTE: A sample time delay (60us) also need to be included in
 	 * conversion time, so the final result is ~= 121.6us.
 	 */
-	IT83XX_ADC_ADCSTS &= ~(1 << 7);
-	IT83XX_ADC_ADCCFG &= ~(1 << 5);
+	IT83XX_ADC_ADCSTS &= ~BIT(7);
+	IT83XX_ADC_ADCCFG &= ~BIT(5);
 	IT83XX_ADC_ADCCTL = 1;
 
 	task_waiting = TASK_ID_INVALID;
diff --git a/chip/it83xx/clock.c b/chip/it83xx/clock.c
index 75c4e1dbeb..fde5045389 100644
--- a/chip/it83xx/clock.c
+++ b/chip/it83xx/clock.c
@@ -62,11 +62,11 @@ struct clock_gate_ctrl {
 static void clock_module_disable(void)
 {
 	/* bit0: FSPI interface tri-state */
-	IT83XX_SMFI_FLHCTRL3R |= (1 << 0);
+	IT83XX_SMFI_FLHCTRL3R |= BIT(0);
 	/* bit7: USB pad power-on disable */
-	IT83XX_GCTRL_PMER2 &= ~(1 << 7);
+	IT83XX_GCTRL_PMER2 &= ~BIT(7);
 	/* bit7: USB debug disable */
-	IT83XX_GCTRL_MCCR &= ~(1 << 7);
+	IT83XX_GCTRL_MCCR &= ~BIT(7);
 	clock_disable_peripheral((CGC_OFFSET_EGPC | CGC_OFFSET_CIR), 0, 0);
 	clock_disable_peripheral((CGC_OFFSET_SMBA | CGC_OFFSET_SMBB |
 		CGC_OFFSET_SMBC | CGC_OFFSET_SMBD | CGC_OFFSET_SMBE |
@@ -146,7 +146,7 @@ void __ram_code clock_ec_pll_ctrl(enum ec_pll_ctrl mode)
 
 void __ram_code clock_pll_changed(void)
 {
-	IT83XX_GCTRL_SSCR &= ~(1 << 0);
+	IT83XX_GCTRL_SSCR &= ~BIT(0);
 	/*
 	 * Update PLL settings.
 	 * Writing data to this register doesn't change the
@@ -199,7 +199,7 @@ static void clock_set_pll(enum pll_freq_idx idx)
 		 * We have to set chip select pin as input mode in order to
 		 * change PLL.
 		 */
-		IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | (1 << 7);
+		IT83XX_GPIO_GPCRM5 = (IT83XX_GPIO_GPCRM5 & ~0xc0) | BIT(7);
 #ifdef IT83XX_ESPI_INHIBIT_CS_BY_PAD_DISABLED
 		/*
 		 * On DX version, we have to disable eSPI pad before changing
@@ -281,10 +281,10 @@ void clock_init(void)
 	clock_module_disable();
 
 #ifdef CONFIG_HOSTCMD_X86
-	IT83XX_WUC_WUESR4 = (1 << 2);
+	IT83XX_WUC_WUESR4 = BIT(2);
 	task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
 	/* bit2, wake-up enable for LPC access */
-	IT83XX_WUC_WUENR4 |= (1 << 2);
+	IT83XX_WUC_WUENR4 |= BIT(2);
 #endif
 }
 
@@ -349,7 +349,7 @@ void clock_refresh_console_in_use(void)
 static void clock_event_timer_clock_change(enum ext_timer_clock_source clock,
 					uint32_t count)
 {
-	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~(1 << 0);
+	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
 	IT83XX_ETWD_ETXPSR(EVENT_EXT_TIMER) = clock;
 	IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = count;
 	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= 0x3;
@@ -370,7 +370,7 @@ static void clock_htimer_enable(void)
 
 static int clock_allow_low_power_idle(void)
 {
-	if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & (1 << 0)))
+	if (!(IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)))
 		return 0;
 
 	if (*et_ctrl_regs[EVENT_EXT_TIMER].isr &
@@ -412,7 +412,7 @@ void __enter_hibernate(uint32_t seconds, uint32_t microseconds)
 		chip_clear_pending_irq(i);
 	}
 	/* bit5: watchdog is disabled. */
-	IT83XX_ETWD_ETWCTRL |= (1 << 5);
+	IT83XX_ETWD_ETWCTRL |= BIT(5);
 	/* Setup GPIOs for hibernate */
 	if (board_hibernate_late)
 		board_hibernate_late();
@@ -501,7 +501,7 @@ defined(CONFIG_HOSTCMD_ESPI)
 #ifdef CONFIG_HOSTCMD_X86
 		/* disable lpc access wui */
 		task_disable_irq(IT83XX_IRQ_WKINTAD);
-		IT83XX_WUC_WUESR4 = (1 << 2);
+		IT83XX_WUC_WUESR4 = BIT(2);
 		task_clear_pending_irq(IT83XX_IRQ_WKINTAD);
 #endif
 		/* disable uart wui */
@@ -534,7 +534,7 @@ void __idle(void)
 		/* Check if the EC can enter deep doze mode or not */
 		if (DEEP_SLEEP_ALLOWED && clock_allow_low_power_idle()) {
 			/* reset low power mode hw timer */
-			IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= (1 << 1);
+			IT83XX_ETWD_ETXCTRL(LOW_POWER_EXT_TIMER) |= BIT(1);
 			sleep_mode_t0 = get_time();
 #ifdef CONFIG_HOSTCMD_X86
 			/* enable lpc access wui */
diff --git a/chip/it83xx/ec2i.c b/chip/it83xx/ec2i.c
index 38216592ad..2cdcb43f8a 100644
--- a/chip/it83xx/ec2i.c
+++ b/chip/it83xx/ec2i.c
@@ -160,9 +160,9 @@ enum ec2i_access {
 
 enum ec2i_status_mask {
 	/* 1: EC read-access is still processing. */
-	EC2I_STATUS_CRIB = (1 << 1),
+	EC2I_STATUS_CRIB = BIT(1),
 	/* 1: EC write-access is still processing with IHD register. */
-	EC2I_STATUS_CWIB = (1 << 2),
+	EC2I_STATUS_CWIB = BIT(2),
 	EC2I_STATUS_ALL  = (EC2I_STATUS_CRIB | EC2I_STATUS_CWIB),
 };
 
@@ -179,7 +179,7 @@ static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data)
 	int rv = EC_ERROR_UNKNOWN;
 
 	/* bit1 : VCC power on */
-	if (IT83XX_SWUC_SWCTL1 & (1 << 1)) {
+	if (IT83XX_SWUC_SWCTL1 & BIT(1)) {
 		/*
 		 * Wait that both CRIB and CWIB bits in IBCTL register
 		 * are cleared.
@@ -191,15 +191,15 @@ static enum ec2i_message ec2i_write_pnpcfg(enum ec2i_access sel, uint8_t data)
 			/* Write the data to IHD register */
 			IT83XX_EC2I_IHD = data;
 			/* Enable EC access to the PNPCFG registers */
-			IT83XX_EC2I_IBMAE |= (1 << 0);
+			IT83XX_EC2I_IBMAE |= BIT(0);
 			/* bit0: EC to I-Bus access enabled. */
-			IT83XX_EC2I_IBCTL |= (1 << 0);
+			IT83XX_EC2I_IBCTL |= BIT(0);
 			/* Wait the CWIB bit in IBCTL cleared. */
 			rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CWIB);
 			/* Disable EC access to the PNPCFG registers. */
-			IT83XX_EC2I_IBMAE &= ~(1 << 0);
+			IT83XX_EC2I_IBMAE &= ~BIT(0);
 			/* Disable EC to I-Bus access. */
-			IT83XX_EC2I_IBCTL &= ~(1 << 0);
+			IT83XX_EC2I_IBCTL &= ~BIT(0);
 		}
 	}
 
@@ -212,7 +212,7 @@ static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel)
 	uint8_t ihd = 0;
 
 	/* bit1 : VCC power on */
-	if (IT83XX_SWUC_SWCTL1 & (1 << 1)) {
+	if (IT83XX_SWUC_SWCTL1 & BIT(1)) {
 		/*
 		 * Wait that both CRIB and CWIB bits in IBCTL register
 		 * are cleared.
@@ -222,19 +222,19 @@ static enum ec2i_message ec2i_read_pnpcfg(enum ec2i_access sel)
 			/* Set indirect host I/O offset. */
 			IT83XX_EC2I_IHIOA = sel;
 			/* Enable EC access to the PNPCFG registers */
-			IT83XX_EC2I_IBMAE |= (1 << 0);
+			IT83XX_EC2I_IBMAE |= BIT(0);
 			/* bit1: a read-action */
-			IT83XX_EC2I_IBCTL |= (1 << 1);
+			IT83XX_EC2I_IBCTL |= BIT(1);
 			/* bit0: EC to I-Bus access enabled. */
-			IT83XX_EC2I_IBCTL |= (1 << 0);
+			IT83XX_EC2I_IBCTL |= BIT(0);
 			/* Wait the CRIB bit in IBCTL cleared. */
 			rv = ec2i_wait_status_bit_cleared(EC2I_STATUS_CRIB);
 			/* Read the data from IHD register */
 			ihd = IT83XX_EC2I_IHD;
 			/* Disable EC access to the PNPCFG registers. */
-			IT83XX_EC2I_IBMAE &= ~(1 << 0);
+			IT83XX_EC2I_IBMAE &= ~BIT(0);
 			/* Disable EC to I-Bus access. */
-			IT83XX_EC2I_IBCTL &= ~(1 << 0);
+			IT83XX_EC2I_IBCTL &= ~BIT(0);
 		}
 	}
 
diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c
index 21e462596b..9e68eedf00 100644
--- a/chip/it83xx/espi.c
+++ b/chip/it83xx/espi.c
@@ -431,7 +431,7 @@ void __ram_code espi_fw_reset_module(void)
 	 * 01b: The VCC power status is treated as power-on.
 	 */
 	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0);
-	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | (1 << 6);
+	IT83XX_GCTRL_RSTS = (IT83XX_GCTRL_RSTS & ~0xc0) | BIT(6);
 }
 #endif
 
@@ -457,9 +457,9 @@ static int espi_get_reset_enable_config(void)
 	 * 10b: espi_reset# is enabled on GPD2.
 	 * 11b: reset is disabled.
 	 */
-	if (espi_rst->port == GPIO_D && espi_rst->mask == (1 << 2)) {
+	if (espi_rst->port == GPIO_D && espi_rst->mask == BIT(2)) {
 		config = IT83XX_GPIO_GCR_LPC_RST_D2;
-	} else if (espi_rst->port == GPIO_B && espi_rst->mask == (1 << 7)) {
+	} else if (espi_rst->port == GPIO_B && espi_rst->mask == BIT(7)) {
 		config = IT83XX_GPIO_GCR_LPC_RST_B7;
 	} else {
 		config = IT83XX_GPIO_GCR_LPC_RST_DISABLE;
@@ -575,10 +575,10 @@ void espi_enable_pad(int enable)
 {
 	if (enable)
 		/* Enable eSPI pad. */
-		IT83XX_ESPI_ESGCTRL2 &= ~(1 << 6);
+		IT83XX_ESPI_ESGCTRL2 &= ~BIT(6);
 	else
 		/* Disable eSPI pad. */
-		IT83XX_ESPI_ESGCTRL2 |= (1 << 6);
+		IT83XX_ESPI_ESGCTRL2 |= BIT(6);
 }
 #endif
 
@@ -593,7 +593,7 @@ void espi_init(void)
 	 * 100b: 66MHz
 	 */
 #ifdef IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE
-	IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | (1 << 2);
+	IT83XX_ESPI_GCAC1 = (IT83XX_ESPI_GCAC1 & ~0x7) | BIT(2);
 #endif
 	/* reset vw_index_flag at initialization */
 	espi_reset_vw_index_flags();
@@ -602,16 +602,16 @@ void espi_init(void)
 	 * bit[3]: The reset source of PNPCFG is RSTPNP bit in RSTCH
 	 * register and WRST#.
 	 */
-	IT83XX_GCTRL_RSTS &= ~(1 << 3);
+	IT83XX_GCTRL_RSTS &= ~BIT(3);
 	task_clear_pending_irq(IT83XX_IRQ_ESPI_VW);
 	/* bit7: VW interrupt enable */
-	IT83XX_ESPI_VWCTRL0 |= (1 << 7);
+	IT83XX_ESPI_VWCTRL0 |= BIT(7);
 	task_enable_irq(IT83XX_IRQ_ESPI_VW);
 
 	/* bit7: eSPI interrupt enable */
-	IT83XX_ESPI_ESGCTRL1 |= (1 << 7);
+	IT83XX_ESPI_ESGCTRL1 |= BIT(7);
 	/* bit4: eSPI to WUC enable */
-	IT83XX_ESPI_ESGCTRL2 |= (1 << 4);
+	IT83XX_ESPI_ESGCTRL2 |= BIT(4);
 	task_enable_irq(IT83XX_IRQ_ESPI);
 
 	/* enable interrupt and reset from eSPI_reset# */
diff --git a/chip/it83xx/gpio.c b/chip/it83xx/gpio.c
index f89f791f11..5c390553ef 100644
--- a/chip/it83xx/gpio.c
+++ b/chip/it83xx/gpio.c
@@ -100,111 +100,111 @@ static const struct {
 	uint8_t wuc_mask;
 } gpio_irqs[] = {
 	/*     irq           gpio_port,gpio_mask,wuc_group,wuc_mask */
-	[IT83XX_IRQ_WKO20] =    {GPIO_D, (1<<0),        2, (1<<0)},
-	[IT83XX_IRQ_WKO21] =    {GPIO_D, (1<<1),        2, (1<<1)},
-	[IT83XX_IRQ_WKO22] =    {GPIO_C, (1<<4),        2, (1<<2)},
-	[IT83XX_IRQ_WKO23] =    {GPIO_C, (1<<6),        2, (1<<3)},
-	[IT83XX_IRQ_WKO24] =    {GPIO_D, (1<<2),        2, (1<<4)},
+	[IT83XX_IRQ_WKO20] =    {GPIO_D, BIT(0),        2, BIT(0)},
+	[IT83XX_IRQ_WKO21] =    {GPIO_D, BIT(1),        2, BIT(1)},
+	[IT83XX_IRQ_WKO22] =    {GPIO_C, BIT(4),        2, BIT(2)},
+	[IT83XX_IRQ_WKO23] =    {GPIO_C, BIT(6),        2, BIT(3)},
+	[IT83XX_IRQ_WKO24] =    {GPIO_D, BIT(2),        2, BIT(4)},
 #ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO40] =    {GPIO_E, (1<<5),        4, (1<<0)},
-	[IT83XX_IRQ_WKO45] =    {GPIO_E, (1<<6),        4, (1<<5)},
-	[IT83XX_IRQ_WKO46] =    {GPIO_E, (1<<7),        4, (1<<6)},
+	[IT83XX_IRQ_WKO40] =    {GPIO_E, BIT(5),        4, BIT(0)},
+	[IT83XX_IRQ_WKO45] =    {GPIO_E, BIT(6),        4, BIT(5)},
+	[IT83XX_IRQ_WKO46] =    {GPIO_E, BIT(7),        4, BIT(6)},
 #endif
-	[IT83XX_IRQ_WKO50] =    {GPIO_K, (1<<0),        5, (1<<0)},
-	[IT83XX_IRQ_WKO51] =    {GPIO_K, (1<<1),        5, (1<<1)},
-	[IT83XX_IRQ_WKO52] =    {GPIO_K, (1<<2),        5, (1<<2)},
-	[IT83XX_IRQ_WKO53] =    {GPIO_K, (1<<3),        5, (1<<3)},
-	[IT83XX_IRQ_WKO54] =    {GPIO_K, (1<<4),        5, (1<<4)},
-	[IT83XX_IRQ_WKO55] =    {GPIO_K, (1<<5),        5, (1<<5)},
-	[IT83XX_IRQ_WKO56] =    {GPIO_K, (1<<6),        5, (1<<6)},
-	[IT83XX_IRQ_WKO57] =    {GPIO_K, (1<<7),        5, (1<<7)},
-	[IT83XX_IRQ_WKO60] =    {GPIO_H, (1<<0),        6, (1<<0)},
-	[IT83XX_IRQ_WKO61] =    {GPIO_H, (1<<1),        6, (1<<1)},
-	[IT83XX_IRQ_WKO62] =    {GPIO_H, (1<<2),        6, (1<<2)},
-	[IT83XX_IRQ_WKO63] =    {GPIO_H, (1<<3),        6, (1<<3)},
-	[IT83XX_IRQ_WKO64] =    {GPIO_F, (1<<4),        6, (1<<4)},
-	[IT83XX_IRQ_WKO65] =    {GPIO_F, (1<<5),        6, (1<<5)},
-	[IT83XX_IRQ_WKO65] =    {GPIO_F, (1<<6),        6, (1<<6)},
-	[IT83XX_IRQ_WKO67] =    {GPIO_F, (1<<7),        6, (1<<7)},
-	[IT83XX_IRQ_WKO70] =    {GPIO_E, (1<<0),        7, (1<<0)},
-	[IT83XX_IRQ_WKO71] =    {GPIO_E, (1<<1),        7, (1<<1)},
-	[IT83XX_IRQ_WKO72] =    {GPIO_E, (1<<2),        7, (1<<2)},
-	[IT83XX_IRQ_WKO73] =    {GPIO_E, (1<<3),        7, (1<<3)},
-	[IT83XX_IRQ_WKO74] =    {GPIO_I, (1<<4),        7, (1<<4)},
-	[IT83XX_IRQ_WKO75] =    {GPIO_I, (1<<5),        7, (1<<5)},
-	[IT83XX_IRQ_WKO76] =    {GPIO_I, (1<<6),        7, (1<<6)},
-	[IT83XX_IRQ_WKO77] =    {GPIO_I, (1<<7),        7, (1<<7)},
-	[IT83XX_IRQ_WKO80] =    {GPIO_A, (1<<3),        8, (1<<0)},
-	[IT83XX_IRQ_WKO81] =    {GPIO_A, (1<<4),        8, (1<<1)},
-	[IT83XX_IRQ_WKO82] =    {GPIO_A, (1<<5),        8, (1<<2)},
-	[IT83XX_IRQ_WKO83] =    {GPIO_A, (1<<6),        8, (1<<3)},
-	[IT83XX_IRQ_WKO84] =    {GPIO_B, (1<<2),        8, (1<<4)},
-	[IT83XX_IRQ_WKO85] =    {GPIO_C, (1<<0),        8, (1<<5)},
-	[IT83XX_IRQ_WKO86] =    {GPIO_C, (1<<7),        8, (1<<6)},
-	[IT83XX_IRQ_WKO87] =    {GPIO_D, (1<<7),        8, (1<<7)},
-	[IT83XX_IRQ_WKO88] =    {GPIO_H, (1<<4),        9, (1<<0)},
-	[IT83XX_IRQ_WKO89] =    {GPIO_H, (1<<5),        9, (1<<1)},
-	[IT83XX_IRQ_WKO90] =    {GPIO_H, (1<<6),        9, (1<<2)},
-	[IT83XX_IRQ_WKO91] =    {GPIO_A, (1<<0),        9, (1<<3)},
-	[IT83XX_IRQ_WKO92] =    {GPIO_A, (1<<1),        9, (1<<4)},
-	[IT83XX_IRQ_WKO93] =    {GPIO_A, (1<<2),        9, (1<<5)},
-	[IT83XX_IRQ_WKO94] =    {GPIO_B, (1<<4),        9, (1<<6)},
-	[IT83XX_IRQ_WKO95] =    {GPIO_C, (1<<2),        9, (1<<7)},
-	[IT83XX_IRQ_WKO96] =    {GPIO_F, (1<<0),        10, (1<<0)},
-	[IT83XX_IRQ_WKO97] =    {GPIO_F, (1<<1),        10, (1<<1)},
-	[IT83XX_IRQ_WKO98] =    {GPIO_F, (1<<2),        10, (1<<2)},
-	[IT83XX_IRQ_WKO99] =    {GPIO_F, (1<<3),        10, (1<<3)},
-	[IT83XX_IRQ_WKO100] =   {GPIO_A, (1<<7),        10, (1<<4)},
-	[IT83XX_IRQ_WKO101] =   {GPIO_B, (1<<0),        10, (1<<5)},
-	[IT83XX_IRQ_WKO102] =   {GPIO_B, (1<<1),        10, (1<<6)},
-	[IT83XX_IRQ_WKO103] =   {GPIO_B, (1<<3),        10, (1<<7)},
-	[IT83XX_IRQ_WKO104] =   {GPIO_B, (1<<5),        11, (1<<0)},
-	[IT83XX_IRQ_WKO105] =   {GPIO_B, (1<<6),        11, (1<<1)},
-	[IT83XX_IRQ_WKO106] =   {GPIO_B, (1<<7),        11, (1<<2)},
-	[IT83XX_IRQ_WKO107] =   {GPIO_C, (1<<1),        11, (1<<3)},
-	[IT83XX_IRQ_WKO108] =   {GPIO_C, (1<<3),        11, (1<<4)},
-	[IT83XX_IRQ_WKO109] =   {GPIO_C, (1<<5),        11, (1<<5)},
-	[IT83XX_IRQ_WKO110] =   {GPIO_D, (1<<3),        11, (1<<6)},
-	[IT83XX_IRQ_WKO111] =   {GPIO_D, (1<<4),        11, (1<<7)},
-	[IT83XX_IRQ_WKO112] =   {GPIO_D, (1<<5),        12, (1<<0)},
-	[IT83XX_IRQ_WKO113] =   {GPIO_D, (1<<6),        12, (1<<1)},
-	[IT83XX_IRQ_WKO114] =   {GPIO_E, (1<<4),        12, (1<<2)},
-	[IT83XX_IRQ_WKO115] =   {GPIO_G, (1<<0),        12, (1<<3)},
-	[IT83XX_IRQ_WKO116] =   {GPIO_G, (1<<1),        12, (1<<4)},
-	[IT83XX_IRQ_WKO117] =   {GPIO_G, (1<<2),        12, (1<<5)},
-	[IT83XX_IRQ_WKO118] =   {GPIO_G, (1<<6),        12, (1<<6)},
-	[IT83XX_IRQ_WKO119] =   {GPIO_I, (1<<0),        12, (1<<7)},
-	[IT83XX_IRQ_WKO120] =   {GPIO_I, (1<<1),        13, (1<<0)},
-	[IT83XX_IRQ_WKO121] =   {GPIO_I, (1<<2),        13, (1<<1)},
-	[IT83XX_IRQ_WKO122] =   {GPIO_I, (1<<3),        13, (1<<2)},
+	[IT83XX_IRQ_WKO50] =    {GPIO_K, BIT(0),        5, BIT(0)},
+	[IT83XX_IRQ_WKO51] =    {GPIO_K, BIT(1),        5, BIT(1)},
+	[IT83XX_IRQ_WKO52] =    {GPIO_K, BIT(2),        5, BIT(2)},
+	[IT83XX_IRQ_WKO53] =    {GPIO_K, BIT(3),        5, BIT(3)},
+	[IT83XX_IRQ_WKO54] =    {GPIO_K, BIT(4),        5, BIT(4)},
+	[IT83XX_IRQ_WKO55] =    {GPIO_K, BIT(5),        5, BIT(5)},
+	[IT83XX_IRQ_WKO56] =    {GPIO_K, BIT(6),        5, BIT(6)},
+	[IT83XX_IRQ_WKO57] =    {GPIO_K, BIT(7),        5, BIT(7)},
+	[IT83XX_IRQ_WKO60] =    {GPIO_H, BIT(0),        6, BIT(0)},
+	[IT83XX_IRQ_WKO61] =    {GPIO_H, BIT(1),        6, BIT(1)},
+	[IT83XX_IRQ_WKO62] =    {GPIO_H, BIT(2),        6, BIT(2)},
+	[IT83XX_IRQ_WKO63] =    {GPIO_H, BIT(3),        6, BIT(3)},
+	[IT83XX_IRQ_WKO64] =    {GPIO_F, BIT(4),        6, BIT(4)},
+	[IT83XX_IRQ_WKO65] =    {GPIO_F, BIT(5),        6, BIT(5)},
+	[IT83XX_IRQ_WKO65] =    {GPIO_F, BIT(6),        6, BIT(6)},
+	[IT83XX_IRQ_WKO67] =    {GPIO_F, BIT(7),        6, BIT(7)},
+	[IT83XX_IRQ_WKO70] =    {GPIO_E, BIT(0),        7, BIT(0)},
+	[IT83XX_IRQ_WKO71] =    {GPIO_E, BIT(1),        7, BIT(1)},
+	[IT83XX_IRQ_WKO72] =    {GPIO_E, BIT(2),        7, BIT(2)},
+	[IT83XX_IRQ_WKO73] =    {GPIO_E, BIT(3),        7, BIT(3)},
+	[IT83XX_IRQ_WKO74] =    {GPIO_I, BIT(4),        7, BIT(4)},
+	[IT83XX_IRQ_WKO75] =    {GPIO_I, BIT(5),        7, BIT(5)},
+	[IT83XX_IRQ_WKO76] =    {GPIO_I, BIT(6),        7, BIT(6)},
+	[IT83XX_IRQ_WKO77] =    {GPIO_I, BIT(7),        7, BIT(7)},
+	[IT83XX_IRQ_WKO80] =    {GPIO_A, BIT(3),        8, BIT(0)},
+	[IT83XX_IRQ_WKO81] =    {GPIO_A, BIT(4),        8, BIT(1)},
+	[IT83XX_IRQ_WKO82] =    {GPIO_A, BIT(5),        8, BIT(2)},
+	[IT83XX_IRQ_WKO83] =    {GPIO_A, BIT(6),        8, BIT(3)},
+	[IT83XX_IRQ_WKO84] =    {GPIO_B, BIT(2),        8, BIT(4)},
+	[IT83XX_IRQ_WKO85] =    {GPIO_C, BIT(0),        8, BIT(5)},
+	[IT83XX_IRQ_WKO86] =    {GPIO_C, BIT(7),        8, BIT(6)},
+	[IT83XX_IRQ_WKO87] =    {GPIO_D, BIT(7),        8, BIT(7)},
+	[IT83XX_IRQ_WKO88] =    {GPIO_H, BIT(4),        9, BIT(0)},
+	[IT83XX_IRQ_WKO89] =    {GPIO_H, BIT(5),        9, BIT(1)},
+	[IT83XX_IRQ_WKO90] =    {GPIO_H, BIT(6),        9, BIT(2)},
+	[IT83XX_IRQ_WKO91] =    {GPIO_A, BIT(0),        9, BIT(3)},
+	[IT83XX_IRQ_WKO92] =    {GPIO_A, BIT(1),        9, BIT(4)},
+	[IT83XX_IRQ_WKO93] =    {GPIO_A, BIT(2),        9, BIT(5)},
+	[IT83XX_IRQ_WKO94] =    {GPIO_B, BIT(4),        9, BIT(6)},
+	[IT83XX_IRQ_WKO95] =    {GPIO_C, BIT(2),        9, BIT(7)},
+	[IT83XX_IRQ_WKO96] =    {GPIO_F, BIT(0),        10, BIT(0)},
+	[IT83XX_IRQ_WKO97] =    {GPIO_F, BIT(1),        10, BIT(1)},
+	[IT83XX_IRQ_WKO98] =    {GPIO_F, BIT(2),        10, BIT(2)},
+	[IT83XX_IRQ_WKO99] =    {GPIO_F, BIT(3),        10, BIT(3)},
+	[IT83XX_IRQ_WKO100] =   {GPIO_A, BIT(7),        10, BIT(4)},
+	[IT83XX_IRQ_WKO101] =   {GPIO_B, BIT(0),        10, BIT(5)},
+	[IT83XX_IRQ_WKO102] =   {GPIO_B, BIT(1),        10, BIT(6)},
+	[IT83XX_IRQ_WKO103] =   {GPIO_B, BIT(3),        10, BIT(7)},
+	[IT83XX_IRQ_WKO104] =   {GPIO_B, BIT(5),        11, BIT(0)},
+	[IT83XX_IRQ_WKO105] =   {GPIO_B, BIT(6),        11, BIT(1)},
+	[IT83XX_IRQ_WKO106] =   {GPIO_B, BIT(7),        11, BIT(2)},
+	[IT83XX_IRQ_WKO107] =   {GPIO_C, BIT(1),        11, BIT(3)},
+	[IT83XX_IRQ_WKO108] =   {GPIO_C, BIT(3),        11, BIT(4)},
+	[IT83XX_IRQ_WKO109] =   {GPIO_C, BIT(5),        11, BIT(5)},
+	[IT83XX_IRQ_WKO110] =   {GPIO_D, BIT(3),        11, BIT(6)},
+	[IT83XX_IRQ_WKO111] =   {GPIO_D, BIT(4),        11, BIT(7)},
+	[IT83XX_IRQ_WKO112] =   {GPIO_D, BIT(5),        12, BIT(0)},
+	[IT83XX_IRQ_WKO113] =   {GPIO_D, BIT(6),        12, BIT(1)},
+	[IT83XX_IRQ_WKO114] =   {GPIO_E, BIT(4),        12, BIT(2)},
+	[IT83XX_IRQ_WKO115] =   {GPIO_G, BIT(0),        12, BIT(3)},
+	[IT83XX_IRQ_WKO116] =   {GPIO_G, BIT(1),        12, BIT(4)},
+	[IT83XX_IRQ_WKO117] =   {GPIO_G, BIT(2),        12, BIT(5)},
+	[IT83XX_IRQ_WKO118] =   {GPIO_G, BIT(6),        12, BIT(6)},
+	[IT83XX_IRQ_WKO119] =   {GPIO_I, BIT(0),        12, BIT(7)},
+	[IT83XX_IRQ_WKO120] =   {GPIO_I, BIT(1),        13, BIT(0)},
+	[IT83XX_IRQ_WKO121] =   {GPIO_I, BIT(2),        13, BIT(1)},
+	[IT83XX_IRQ_WKO122] =   {GPIO_I, BIT(3),        13, BIT(2)},
 #ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO123] =   {GPIO_G, (1<<3),        13, (1<<3)},
-	[IT83XX_IRQ_WKO124] =   {GPIO_G, (1<<4),        13, (1<<4)},
-	[IT83XX_IRQ_WKO125] =   {GPIO_G, (1<<5),        13, (1<<5)},
-	[IT83XX_IRQ_WKO126] =   {GPIO_G, (1<<7),        13, (1<<6)},
+	[IT83XX_IRQ_WKO123] =   {GPIO_G, BIT(3),        13, BIT(3)},
+	[IT83XX_IRQ_WKO124] =   {GPIO_G, BIT(4),        13, BIT(4)},
+	[IT83XX_IRQ_WKO125] =   {GPIO_G, BIT(5),        13, BIT(5)},
+	[IT83XX_IRQ_WKO126] =   {GPIO_G, BIT(7),        13, BIT(6)},
 #endif
-	[IT83XX_IRQ_WKO128] =   {GPIO_J, (1<<0),        14, (1<<0)},
-	[IT83XX_IRQ_WKO129] =   {GPIO_J, (1<<1),        14, (1<<1)},
-	[IT83XX_IRQ_WKO130] =   {GPIO_J, (1<<2),        14, (1<<2)},
-	[IT83XX_IRQ_WKO131] =   {GPIO_J, (1<<3),        14, (1<<3)},
-	[IT83XX_IRQ_WKO132] =   {GPIO_J, (1<<4),        14, (1<<4)},
-	[IT83XX_IRQ_WKO133] =   {GPIO_J, (1<<5),        14, (1<<5)},
-	[IT83XX_IRQ_WKO136] =   {GPIO_L, (1<<0),        15, (1<<0)},
-	[IT83XX_IRQ_WKO137] =   {GPIO_L, (1<<1),        15, (1<<1)},
-	[IT83XX_IRQ_WKO138] =   {GPIO_L, (1<<2),        15, (1<<2)},
-	[IT83XX_IRQ_WKO139] =   {GPIO_L, (1<<3),        15, (1<<3)},
-	[IT83XX_IRQ_WKO140] =   {GPIO_L, (1<<4),        15, (1<<4)},
-	[IT83XX_IRQ_WKO141] =   {GPIO_L, (1<<5),        15, (1<<5)},
-	[IT83XX_IRQ_WKO142] =   {GPIO_L, (1<<6),        15, (1<<6)},
-	[IT83XX_IRQ_WKO143] =   {GPIO_L, (1<<7),        15, (1<<7)},
+	[IT83XX_IRQ_WKO128] =   {GPIO_J, BIT(0),        14, BIT(0)},
+	[IT83XX_IRQ_WKO129] =   {GPIO_J, BIT(1),        14, BIT(1)},
+	[IT83XX_IRQ_WKO130] =   {GPIO_J, BIT(2),        14, BIT(2)},
+	[IT83XX_IRQ_WKO131] =   {GPIO_J, BIT(3),        14, BIT(3)},
+	[IT83XX_IRQ_WKO132] =   {GPIO_J, BIT(4),        14, BIT(4)},
+	[IT83XX_IRQ_WKO133] =   {GPIO_J, BIT(5),        14, BIT(5)},
+	[IT83XX_IRQ_WKO136] =   {GPIO_L, BIT(0),        15, BIT(0)},
+	[IT83XX_IRQ_WKO137] =   {GPIO_L, BIT(1),        15, BIT(1)},
+	[IT83XX_IRQ_WKO138] =   {GPIO_L, BIT(2),        15, BIT(2)},
+	[IT83XX_IRQ_WKO139] =   {GPIO_L, BIT(3),        15, BIT(3)},
+	[IT83XX_IRQ_WKO140] =   {GPIO_L, BIT(4),        15, BIT(4)},
+	[IT83XX_IRQ_WKO141] =   {GPIO_L, BIT(5),        15, BIT(5)},
+	[IT83XX_IRQ_WKO142] =   {GPIO_L, BIT(6),        15, BIT(6)},
+	[IT83XX_IRQ_WKO143] =   {GPIO_L, BIT(7),        15, BIT(7)},
 #ifdef IT83XX_GPIO_INT_FLEXIBLE
-	[IT83XX_IRQ_WKO144] =   {GPIO_M, (1<<0),        16, (1<<0)},
-	[IT83XX_IRQ_WKO145] =   {GPIO_M, (1<<1),        16, (1<<1)},
-	[IT83XX_IRQ_WKO146] =   {GPIO_M, (1<<2),        16, (1<<2)},
-	[IT83XX_IRQ_WKO147] =   {GPIO_M, (1<<3),        16, (1<<3)},
-	[IT83XX_IRQ_WKO148] =   {GPIO_M, (1<<4),        16, (1<<4)},
-	[IT83XX_IRQ_WKO149] =   {GPIO_M, (1<<5),        16, (1<<5)},
-	[IT83XX_IRQ_WKO150] =   {GPIO_M, (1<<6),        16, (1<<6)},
+	[IT83XX_IRQ_WKO144] =   {GPIO_M, BIT(0),        16, BIT(0)},
+	[IT83XX_IRQ_WKO145] =   {GPIO_M, BIT(1),        16, BIT(1)},
+	[IT83XX_IRQ_WKO146] =   {GPIO_M, BIT(2),        16, BIT(2)},
+	[IT83XX_IRQ_WKO147] =   {GPIO_M, BIT(3),        16, BIT(3)},
+	[IT83XX_IRQ_WKO148] =   {GPIO_M, BIT(4),        16, BIT(4)},
+	[IT83XX_IRQ_WKO149] =   {GPIO_M, BIT(5),        16, BIT(5)},
+	[IT83XX_IRQ_WKO150] =   {GPIO_M, BIT(6),        16, BIT(6)},
 #endif
 	[IT83XX_IRQ_COUNT-1] =  {0,           0,         0,      0},
 };
@@ -238,119 +238,119 @@ struct gpio_1p8v_t {
 
 static const struct gpio_1p8v_t gpio_1p8v_sel[GPIO_PORT_COUNT][8] = {
 #ifdef IT83XX_GPIO_1P8V_PIN_EXTENDED
-	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, (1 << 0)},
-		     [5] = {&IT83XX_GPIO_GRC24, (1 << 1)},
-		     [6] = {&IT83XX_GPIO_GRC24, (1 << 5)},
-		     [7] = {&IT83XX_GPIO_GRC24, (1 << 6)} },
-	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, (1 << 1)},
-		     [4] = {&IT83XX_GPIO_GRC22, (1 << 0)},
-		     [5] = {&IT83XX_GPIO_GRC19, (1 << 7)},
-		     [6] = {&IT83XX_GPIO_GRC19, (1 << 6)},
-		     [7] = {&IT83XX_GPIO_GRC24, (1 << 4)} },
-	[GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, (1 << 7)},
-		     [1] = {&IT83XX_GPIO_GRC19, (1 << 5)},
-		     [2] = {&IT83XX_GPIO_GRC19, (1 << 4)},
-		     [4] = {&IT83XX_GPIO_GRC24, (1 << 2)},
-		     [6] = {&IT83XX_GPIO_GRC24, (1 << 3)},
-		     [7] = {&IT83XX_GPIO_GRC19, (1 << 3)} },
-	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, (1 << 2)},
-		     [1] = {&IT83XX_GPIO_GRC19, (1 << 1)},
-		     [2] = {&IT83XX_GPIO_GRC19, (1 << 0)},
-		     [3] = {&IT83XX_GPIO_GRC20, (1 << 7)},
-		     [4] = {&IT83XX_GPIO_GRC20, (1 << 6)},
-		     [5] = {&IT83XX_GPIO_GRC22, (1 << 4)},
-		     [6] = {&IT83XX_GPIO_GRC22, (1 << 5)},
-		     [7] = {&IT83XX_GPIO_GRC22, (1 << 6)} },
-	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, (1 << 5)},
-		     [1] = {&IT83XX_GPIO_GCR28, (1 << 6)},
-		     [2] = {&IT83XX_GPIO_GCR28, (1 << 7)},
-		     [4] = {&IT83XX_GPIO_GRC22, (1 << 2)},
-		     [5] = {&IT83XX_GPIO_GRC22, (1 << 3)},
-		     [6] = {&IT83XX_GPIO_GRC20, (1 << 4)},
-		     [7] = {&IT83XX_GPIO_GRC20, (1 << 3)} },
-	[GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, (1 << 4)},
-		     [1] = {&IT83XX_GPIO_GCR28, (1 << 5)},
-		     [2] = {&IT83XX_GPIO_GRC20, (1 << 2)},
-		     [3] = {&IT83XX_GPIO_GRC20, (1 << 1)},
-		     [4] = {&IT83XX_GPIO_GRC20, (1 << 0)},
-		     [5] = {&IT83XX_GPIO_GRC21, (1 << 7)},
-		     [6] = {&IT83XX_GPIO_GRC21, (1 << 6)},
-		     [7] = {&IT83XX_GPIO_GRC21, (1 << 5)} },
-	[GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, (1 << 2)},
-		     [1] = {&IT83XX_GPIO_GRC21, (1 << 4)},
-		     [2] = {&IT83XX_GPIO_GCR28, (1 << 3)},
-		     [6] = {&IT83XX_GPIO_GRC21, (1 << 3)} },
-	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, (1 << 2)},
-		     [1] = {&IT83XX_GPIO_GRC21, (1 << 1)},
-		     [2] = {&IT83XX_GPIO_GRC21, (1 << 0)},
-		     [5] = {&IT83XX_GPIO_GCR27, (1 << 7)},
-		     [6] = {&IT83XX_GPIO_GCR28, (1 << 0)} },
-	[GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, (1 << 3)},
-		     [1] = {&IT83XX_GPIO_GRC23, (1 << 4)},
-		     [2] = {&IT83XX_GPIO_GRC23, (1 << 5)},
-		     [3] = {&IT83XX_GPIO_GRC23, (1 << 6)},
-		     [4] = {&IT83XX_GPIO_GRC23, (1 << 7)},
-		     [5] = {&IT83XX_GPIO_GCR27, (1 << 4)},
-		     [6] = {&IT83XX_GPIO_GCR27, (1 << 5)},
-		     [7] = {&IT83XX_GPIO_GCR27, (1 << 6)} },
-	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, (1 << 0)},
-		     [1] = {&IT83XX_GPIO_GRC23, (1 << 1)},
-		     [2] = {&IT83XX_GPIO_GRC23, (1 << 2)},
-		     [3] = {&IT83XX_GPIO_GRC23, (1 << 3)},
-		     [4] = {&IT83XX_GPIO_GCR27, (1 << 0)},
-		     [5] = {&IT83XX_GPIO_GCR27, (1 << 1)},
-		     [6] = {&IT83XX_GPIO_GCR27, (1 << 2)} },
-	[GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, (1 << 0)},
-		     [1] = {&IT83XX_GPIO_GCR26, (1 << 1)},
-		     [2] = {&IT83XX_GPIO_GCR26, (1 << 2)},
-		     [3] = {&IT83XX_GPIO_GCR26, (1 << 3)},
-		     [4] = {&IT83XX_GPIO_GCR26, (1 << 4)},
-		     [5] = {&IT83XX_GPIO_GCR26, (1 << 5)},
-		     [6] = {&IT83XX_GPIO_GCR26, (1 << 6)},
-		     [7] = {&IT83XX_GPIO_GCR26, (1 << 7)} },
-	[GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, (1 << 0)},
-		     [1] = {&IT83XX_GPIO_GCR25, (1 << 1)},
-		     [2] = {&IT83XX_GPIO_GCR25, (1 << 2)},
-		     [3] = {&IT83XX_GPIO_GCR25, (1 << 3)},
-		     [4] = {&IT83XX_GPIO_GCR25, (1 << 4)},
-		     [5] = {&IT83XX_GPIO_GCR25, (1 << 5)},
-		     [6] = {&IT83XX_GPIO_GCR25, (1 << 6)},
-		     [7] = {&IT83XX_GPIO_GCR25, (1 << 7)} },
+	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
+		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)},
+		     [6] = {&IT83XX_GPIO_GRC24, BIT(5)},
+		     [7] = {&IT83XX_GPIO_GRC24, BIT(6)} },
+	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
+		     [4] = {&IT83XX_GPIO_GRC22, BIT(0)},
+		     [5] = {&IT83XX_GPIO_GRC19, BIT(7)},
+		     [6] = {&IT83XX_GPIO_GRC19, BIT(6)},
+		     [7] = {&IT83XX_GPIO_GRC24, BIT(4)} },
+	[GPIO_C] = { [0] = {&IT83XX_GPIO_GRC22, BIT(7)},
+		     [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
+		     [2] = {&IT83XX_GPIO_GRC19, BIT(4)},
+		     [4] = {&IT83XX_GPIO_GRC24, BIT(2)},
+		     [6] = {&IT83XX_GPIO_GRC24, BIT(3)},
+		     [7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
+	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
+		     [1] = {&IT83XX_GPIO_GRC19, BIT(1)},
+		     [2] = {&IT83XX_GPIO_GRC19, BIT(0)},
+		     [3] = {&IT83XX_GPIO_GRC20, BIT(7)},
+		     [4] = {&IT83XX_GPIO_GRC20, BIT(6)},
+		     [5] = {&IT83XX_GPIO_GRC22, BIT(4)},
+		     [6] = {&IT83XX_GPIO_GRC22, BIT(5)},
+		     [7] = {&IT83XX_GPIO_GRC22, BIT(6)} },
+	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
+		     [1] = {&IT83XX_GPIO_GCR28, BIT(6)},
+		     [2] = {&IT83XX_GPIO_GCR28, BIT(7)},
+		     [4] = {&IT83XX_GPIO_GRC22, BIT(2)},
+		     [5] = {&IT83XX_GPIO_GRC22, BIT(3)},
+		     [6] = {&IT83XX_GPIO_GRC20, BIT(4)},
+		     [7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
+	[GPIO_F] = { [0] = {&IT83XX_GPIO_GCR28, BIT(4)},
+		     [1] = {&IT83XX_GPIO_GCR28, BIT(5)},
+		     [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
+		     [3] = {&IT83XX_GPIO_GRC20, BIT(1)},
+		     [4] = {&IT83XX_GPIO_GRC20, BIT(0)},
+		     [5] = {&IT83XX_GPIO_GRC21, BIT(7)},
+		     [6] = {&IT83XX_GPIO_GRC21, BIT(6)},
+		     [7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
+	[GPIO_G] = { [0] = {&IT83XX_GPIO_GCR28, BIT(2)},
+		     [1] = {&IT83XX_GPIO_GRC21, BIT(4)},
+		     [2] = {&IT83XX_GPIO_GCR28, BIT(3)},
+		     [6] = {&IT83XX_GPIO_GRC21, BIT(3)} },
+	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
+		     [1] = {&IT83XX_GPIO_GRC21, BIT(1)},
+		     [2] = {&IT83XX_GPIO_GRC21, BIT(0)},
+		     [5] = {&IT83XX_GPIO_GCR27, BIT(7)},
+		     [6] = {&IT83XX_GPIO_GCR28, BIT(0)} },
+	[GPIO_I] = { [0] = {&IT83XX_GPIO_GCR27, BIT(3)},
+		     [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
+		     [2] = {&IT83XX_GPIO_GRC23, BIT(5)},
+		     [3] = {&IT83XX_GPIO_GRC23, BIT(6)},
+		     [4] = {&IT83XX_GPIO_GRC23, BIT(7)},
+		     [5] = {&IT83XX_GPIO_GCR27, BIT(4)},
+		     [6] = {&IT83XX_GPIO_GCR27, BIT(5)},
+		     [7] = {&IT83XX_GPIO_GCR27, BIT(6)} },
+	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
+		     [1] = {&IT83XX_GPIO_GRC23, BIT(1)},
+		     [2] = {&IT83XX_GPIO_GRC23, BIT(2)},
+		     [3] = {&IT83XX_GPIO_GRC23, BIT(3)},
+		     [4] = {&IT83XX_GPIO_GCR27, BIT(0)},
+		     [5] = {&IT83XX_GPIO_GCR27, BIT(1)},
+		     [6] = {&IT83XX_GPIO_GCR27, BIT(2)} },
+	[GPIO_K] = { [0] = {&IT83XX_GPIO_GCR26, BIT(0)},
+		     [1] = {&IT83XX_GPIO_GCR26, BIT(1)},
+		     [2] = {&IT83XX_GPIO_GCR26, BIT(2)},
+		     [3] = {&IT83XX_GPIO_GCR26, BIT(3)},
+		     [4] = {&IT83XX_GPIO_GCR26, BIT(4)},
+		     [5] = {&IT83XX_GPIO_GCR26, BIT(5)},
+		     [6] = {&IT83XX_GPIO_GCR26, BIT(6)},
+		     [7] = {&IT83XX_GPIO_GCR26, BIT(7)} },
+	[GPIO_L] = { [0] = {&IT83XX_GPIO_GCR25, BIT(0)},
+		     [1] = {&IT83XX_GPIO_GCR25, BIT(1)},
+		     [2] = {&IT83XX_GPIO_GCR25, BIT(2)},
+		     [3] = {&IT83XX_GPIO_GCR25, BIT(3)},
+		     [4] = {&IT83XX_GPIO_GCR25, BIT(4)},
+		     [5] = {&IT83XX_GPIO_GCR25, BIT(5)},
+		     [6] = {&IT83XX_GPIO_GCR25, BIT(6)},
+		     [7] = {&IT83XX_GPIO_GCR25, BIT(7)} },
 #else
-	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, (1 << 0)},
-		     [5] = {&IT83XX_GPIO_GRC24, (1 << 1)} },
-	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, (1 << 1)},
-		     [4] = {&IT83XX_GPIO_GRC22, (1 << 0)},
-		     [5] = {&IT83XX_GPIO_GRC19, (1 << 7)},
-		     [6] = {&IT83XX_GPIO_GRC19, (1 << 6)} },
-	[GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, (1 << 5)},
-		     [2] = {&IT83XX_GPIO_GRC19, (1 << 4)},
-		     [7] = {&IT83XX_GPIO_GRC19, (1 << 3)} },
-	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, (1 << 2)},
-		     [1] = {&IT83XX_GPIO_GRC19, (1 << 1)},
-		     [2] = {&IT83XX_GPIO_GRC19, (1 << 0)},
-		     [3] = {&IT83XX_GPIO_GRC20, (1 << 7)},
-		     [4] = {&IT83XX_GPIO_GRC20, (1 << 6)} },
-	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, (1 << 5)},
-		     [6] = {&IT83XX_GPIO_GRC20, (1 << 4)},
-		     [7] = {&IT83XX_GPIO_GRC20, (1 << 3)} },
-	[GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, (1 << 2)},
-		     [3] = {&IT83XX_GPIO_GRC20, (1 << 1)},
-		     [4] = {&IT83XX_GPIO_GRC20, (1 << 0)},
-		     [5] = {&IT83XX_GPIO_GRC21, (1 << 7)},
-		     [6] = {&IT83XX_GPIO_GRC21, (1 << 6)},
-		     [7] = {&IT83XX_GPIO_GRC21, (1 << 5)} },
-	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, (1 << 2)},
-		     [1] = {&IT83XX_GPIO_GRC21, (1 << 1)},
-		     [2] = {&IT83XX_GPIO_GRC21, (1 << 0)} },
-	[GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, (1 << 4)},
-		     [2] = {&IT83XX_GPIO_GRC23, (1 << 5)},
-		     [3] = {&IT83XX_GPIO_GRC23, (1 << 6)},
-		     [4] = {&IT83XX_GPIO_GRC23, (1 << 7)} },
-	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, (1 << 0)},
-		     [1] = {&IT83XX_GPIO_GRC23, (1 << 1)},
-		     [2] = {&IT83XX_GPIO_GRC23, (1 << 2)},
-		     [3] = {&IT83XX_GPIO_GRC23, (1 << 3)} },
+	[GPIO_A] = { [4] = {&IT83XX_GPIO_GRC24, BIT(0)},
+		     [5] = {&IT83XX_GPIO_GRC24, BIT(1)} },
+	[GPIO_B] = { [3] = {&IT83XX_GPIO_GRC22, BIT(1)},
+		     [4] = {&IT83XX_GPIO_GRC22, BIT(0)},
+		     [5] = {&IT83XX_GPIO_GRC19, BIT(7)},
+		     [6] = {&IT83XX_GPIO_GRC19, BIT(6)} },
+	[GPIO_C] = { [1] = {&IT83XX_GPIO_GRC19, BIT(5)},
+		     [2] = {&IT83XX_GPIO_GRC19, BIT(4)},
+		     [7] = {&IT83XX_GPIO_GRC19, BIT(3)} },
+	[GPIO_D] = { [0] = {&IT83XX_GPIO_GRC19, BIT(2)},
+		     [1] = {&IT83XX_GPIO_GRC19, BIT(1)},
+		     [2] = {&IT83XX_GPIO_GRC19, BIT(0)},
+		     [3] = {&IT83XX_GPIO_GRC20, BIT(7)},
+		     [4] = {&IT83XX_GPIO_GRC20, BIT(6)} },
+	[GPIO_E] = { [0] = {&IT83XX_GPIO_GRC20, BIT(5)},
+		     [6] = {&IT83XX_GPIO_GRC20, BIT(4)},
+		     [7] = {&IT83XX_GPIO_GRC20, BIT(3)} },
+	[GPIO_F] = { [2] = {&IT83XX_GPIO_GRC20, BIT(2)},
+		     [3] = {&IT83XX_GPIO_GRC20, BIT(1)},
+		     [4] = {&IT83XX_GPIO_GRC20, BIT(0)},
+		     [5] = {&IT83XX_GPIO_GRC21, BIT(7)},
+		     [6] = {&IT83XX_GPIO_GRC21, BIT(6)},
+		     [7] = {&IT83XX_GPIO_GRC21, BIT(5)} },
+	[GPIO_H] = { [0] = {&IT83XX_GPIO_GRC21, BIT(2)},
+		     [1] = {&IT83XX_GPIO_GRC21, BIT(1)},
+		     [2] = {&IT83XX_GPIO_GRC21, BIT(0)} },
+	[GPIO_I] = { [1] = {&IT83XX_GPIO_GRC23, BIT(4)},
+		     [2] = {&IT83XX_GPIO_GRC23, BIT(5)},
+		     [3] = {&IT83XX_GPIO_GRC23, BIT(6)},
+		     [4] = {&IT83XX_GPIO_GRC23, BIT(7)} },
+	[GPIO_J] = { [0] = {&IT83XX_GPIO_GRC23, BIT(0)},
+		     [1] = {&IT83XX_GPIO_GRC23, BIT(1)},
+		     [2] = {&IT83XX_GPIO_GRC23, BIT(2)},
+		     [3] = {&IT83XX_GPIO_GRC23, BIT(3)} },
 #endif
 };
 
diff --git a/chip/it83xx/hwtimer.c b/chip/it83xx/hwtimer.c
index e65fea38fa..ecfbcf7be6 100644
--- a/chip/it83xx/hwtimer.c
+++ b/chip/it83xx/hwtimer.c
@@ -81,7 +81,7 @@ static void free_run_timer_overflow(void)
 		/* set timer counter register */
 		IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff;
 		/* bit[1], timer reset */
-		IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 1);
+		IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1);
 	}
 	/* w/c interrupt status */
 	task_clear_pending_irq(et_ctrl_regs[FREE_EXT_TIMER_H].irq);
@@ -114,14 +114,14 @@ void __hw_clock_source_set(uint32_t ts)
 	/* counting down timer, microseconds to timer counter register */
 	IT83XX_ETWD_ETXCNTLR(FREE_EXT_TIMER_H) = 0xffffffff - ts;
 	/* bit[1], timer reset */
-	IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 1);
+	IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(1);
 }
 
 void __hw_clock_event_set(uint32_t deadline)
 {
 	uint32_t wait;
 	/* bit0, disable event timer */
-	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~(1 << 0);
+	IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) &= ~BIT(0);
 	/* w/c interrupt status */
 	event_timer_clear_pending_isr();
 	/* microseconds to timer counter */
@@ -139,7 +139,7 @@ uint32_t __hw_clock_event_get(void)
 	uint32_t next_event_us = __hw_clock_source_read();
 
 	/* bit0, event timer is enabled */
-	if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & (1 << 0)) {
+	if (IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) & BIT(0)) {
 		/* timer counter observation value to microseconds */
 		next_event_us += EVENT_TIMER_COUNT_TO_US(
 #ifdef IT83XX_EXT_OBSERVATION_REG_READ_TWO_TIMES
@@ -161,7 +161,7 @@ void __hw_clock_event_clear(void)
 int __hw_clock_source_init(uint32_t start_t)
 {
 	/* bit3, timer 3 and timer 4 combinational mode */
-	IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= (1 << 3);
+	IT83XX_ETWD_ETXCTRL(FREE_EXT_TIMER_L) |= BIT(3);
 	/* init free running timer (timer 4, TIMER_H), clock source is 8mhz */
 	ext_timer_ms(FREE_EXT_TIMER_H, EXT_PSR_8M_HZ, 0, 1, 0xffffffff, 1, 1);
 	/* 1us counter setting (timer 3, TIMER_L) */
@@ -181,7 +181,7 @@ static void __hw_clock_source_irq(void)
 	/* SW/HW interrupt of event timer. */
 	if (irq == et_ctrl_regs[EVENT_EXT_TIMER].irq) {
 		IT83XX_ETWD_ETXCNTLR(EVENT_EXT_TIMER) = 0xffffffff;
-		IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= (1 << 1);
+		IT83XX_ETWD_ETXCTRL(EVENT_EXT_TIMER) |= BIT(1);
 		event_timer_clear_pending_isr();
 		process_timers(0);
 		return;
diff --git a/chip/it83xx/i2c.c b/chip/it83xx/i2c.c
index a88599b380..56f805b9f6 100644
--- a/chip/it83xx/i2c.c
+++ b/chip/it83xx/i2c.c
@@ -292,7 +292,7 @@ static void i2c_pio_trans_data(int p, enum enhanced_i2c_transfer_direct direct,
 	if (first_byte) {
 		/* First byte must be slave address. */
 		IT83XX_I2C_DTR(p_ch) =
-			data | (direct == RX_DIRECT ? (1 << 0) : 0);
+			data | (direct == RX_DIRECT ? BIT(0) : 0);
 		/* start or repeat start signal. */
 		IT83XX_I2C_CTR(p_ch) = E_START_ID;
 	} else {
@@ -457,7 +457,7 @@ static void enhanced_i2c_start(int p)
 	 */
 	IT83XX_I2C_TOR(p_ch) = I2C_CLK_LOW_TIMEOUT;
 	/* bit1: Enable enhanced i2c module */
-	IT83XX_I2C_CTR1(p_ch) = (1 << 1);
+	IT83XX_I2C_CTR1(p_ch) = BIT(1);
 }
 
 static int enhanced_i2c_tran_write(int p)
diff --git a/chip/it83xx/keyboard_raw.c b/chip/it83xx/keyboard_raw.c
index 9c5d1028ae..d6d01e1247 100644
--- a/chip/it83xx/keyboard_raw.c
+++ b/chip/it83xx/keyboard_raw.c
@@ -31,7 +31,7 @@ void keyboard_raw_init(void)
 
 #ifdef CONFIG_KEYBOARD_COL2_INVERTED
 	/* KSO[2] is high, others are low. */
-	IT83XX_KBS_KSOL = (1 << 2);
+	IT83XX_KBS_KSOL = BIT(2);
 #else
 	/* KSO[7:0] pins low. */
 	IT83XX_KBS_KSOL = 0x00;
@@ -81,7 +81,7 @@ test_mockable void keyboard_raw_drive_column(int col)
 
 #ifdef CONFIG_KEYBOARD_COL2_INVERTED
 	/* KSO[2] is inverted. */
-	mask ^= (1 << 2);
+	mask ^= BIT(2);
 #endif
 	IT83XX_KBS_KSOL = mask & 0xff;
 	IT83XX_KBS_KSOH1 = (mask >> 8) & 0xff;
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c
index 5765788718..5ca7cf91b9 100644
--- a/chip/it83xx/lpc.c
+++ b/chip/it83xx/lpc.c
@@ -103,7 +103,7 @@ static void pm_put_data_out(enum lpc_pm_ch ch, uint8_t out)
 static void pm_clear_ibf(enum lpc_pm_ch ch)
 {
 	/* bit7, write-1 clear IBF */
-	IT83XX_PMC_PMIE(ch) |= (1 << 7);
+	IT83XX_PMC_PMIE(ch) |= BIT(7);
 }
 
 #ifdef CONFIG_KEYBOARD_IRQ_GPIO
@@ -340,8 +340,8 @@ void lpc_keyboard_clear_buffer(void)
 	uint32_t int_mask = get_int_mask();
 	interrupt_disable();
 	/* bit6, write-1 clear OBF */
-	IT83XX_KBC_KBHICR |= (1 << 6);
-	IT83XX_KBC_KBHICR &= ~(1 << 6);
+	IT83XX_KBC_KBHICR |= BIT(6);
+	IT83XX_KBC_KBHICR &= ~BIT(6);
 	set_int_mask(int_mask);
 }
 
@@ -392,8 +392,8 @@ void lpc_kbc_ibf_interrupt(void)
 		keyboard_host_write(IT83XX_KBC_KBHIDIR,
 			(IT83XX_KBC_KBHISR & 0x08) ? 1 : 0);
 		/* bit7, write-1 clear IBF */
-		IT83XX_KBC_KBHICR |= (1 << 7);
-		IT83XX_KBC_KBHICR &= ~(1 << 7);
+		IT83XX_KBC_KBHICR |= BIT(7);
+		IT83XX_KBC_KBHICR &= ~BIT(7);
 	}
 
 	task_clear_pending_irq(IT83XX_IRQ_KBC_IN);
@@ -745,7 +745,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args)
 	struct ec_response_get_protocol_info *r = args->response;
 
 	memset(r, 0, sizeof(*r));
-	r->protocol_versions = (1 << 3);
+	r->protocol_versions = BIT(3);
 	r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE;
 	r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE;
 	r->flags = 0;
diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h
index 8d2d8016bb..6414ec9d16 100644
--- a/chip/it83xx/registers.h
+++ b/chip/it83xx/registers.h
@@ -1179,26 +1179,26 @@ enum i2c_channels {
 #define IT83XX_USBPD_BASE(port)   (0x00F03700 + (0x100 * (port)))
 
 #define IT83XX_USBPD_GCR(p)       REG8(IT83XX_USBPD_BASE(p)+0x0)
-#define USBPD_REG_MASK_SW_RESET_BIT           (1 << 7)
-#define USBPD_REG_MASK_TYPE_C_DETECT_RESET    (1 << 6)
-#define USBPD_REG_MASK_BMC_PHY                (1 << 4)
-#define USBPD_REG_MASK_AUTO_SEND_SW_RESET     (1 << 3)
-#define USBPD_REG_MASK_AUTO_SEND_HW_RESET     (1 << 2)
-#define USBPD_REG_MASK_SNIFFER_MODE           (1 << 1)
-#define USBPD_REG_MASK_GLOBAL_ENABLE          (1 << 0)
+#define USBPD_REG_MASK_SW_RESET_BIT           BIT(7)
+#define USBPD_REG_MASK_TYPE_C_DETECT_RESET    BIT(6)
+#define USBPD_REG_MASK_BMC_PHY                BIT(4)
+#define USBPD_REG_MASK_AUTO_SEND_SW_RESET     BIT(3)
+#define USBPD_REG_MASK_AUTO_SEND_HW_RESET     BIT(2)
+#define USBPD_REG_MASK_SNIFFER_MODE           BIT(1)
+#define USBPD_REG_MASK_GLOBAL_ENABLE          BIT(0)
 #define IT83XX_USBPD_PDMSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x01)
-#define USBPD_REG_MASK_SOPPP_ENABLE           (1 << 7)
-#define USBPD_REG_MASK_SOPP_ENABLE            (1 << 6)
-#define USBPD_REG_MASK_SOP_ENABLE             (1 << 5)
+#define USBPD_REG_MASK_SOPPP_ENABLE           BIT(7)
+#define USBPD_REG_MASK_SOPP_ENABLE            BIT(6)
+#define USBPD_REG_MASK_SOP_ENABLE             BIT(5)
 #define IT83XX_USBPD_CCGCR(p)     REG8(IT83XX_USBPD_BASE(p)+0x04)
-#define USBPD_REG_MASK_DISABLE_CC             (1 << 4)
+#define USBPD_REG_MASK_DISABLE_CC             BIT(4)
 #define IT83XX_USBPD_CCCSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x05)
 #ifdef IT83XX_USBPD_CC_VOLTAGE_DETECTOR_INDEPENDENT
-#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT  ((1 << 3) | (1 << 1))
-#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT  ((1 << 7) | (1 << 5))
+#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT  (BIT(3) | BIT(1))
+#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT  (BIT(7) | BIT(5))
 #else
-#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT  (1 << 3)
-#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT  (1 << 7)
+#define IT83XX_USBPD_REG_MASK_CC1_DISCONNECT  BIT(3)
+#define IT83XX_USBPD_REG_MASK_CC2_DISCONNECT  BIT(7)
 #endif
 #define USBPD_CC1_DISCONNECTED(p) \
 	((IT83XX_USBPD_CCCSR(p) | IT83XX_USBPD_REG_MASK_CC1_DISCONNECT) & \
@@ -1208,35 +1208,35 @@ enum i2c_channels {
 	~IT83XX_USBPD_REG_MASK_CC1_DISCONNECT)
 
 #define IT83XX_USBPD_CCPSR(p)     REG8(IT83XX_USBPD_BASE(p)+0x06)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC2   (1 << 5)
-#define USBPD_REG_MASK_DISCONNECT_POWER_CC1   (1 << 1)
+#define USBPD_REG_MASK_DISCONNECT_POWER_CC2   BIT(5)
+#define USBPD_REG_MASK_DISCONNECT_POWER_CC1   BIT(1)
 #define IT83XX_USBPD_DFPVDR(p)    REG8(IT83XX_USBPD_BASE(p)+0x08)
 #define IT83XX_USBPD_UFPVDR(p)    REG8(IT83XX_USBPD_BASE(p)+0x09)
 #define IT83XX_USBPD_CCADCR(p)    REG8(IT83XX_USBPD_BASE(p)+0x0C)
 #define IT83XX_USBPD_ISR(p)       REG8(IT83XX_USBPD_BASE(p)+0x14)
-#define USBPD_REG_MASK_TYPE_C_DETECT           (1 << 7)
-#define USBPD_REG_MASK_CABLE_RESET_DETECT      (1 << 6)
-#define USBPD_REG_MASK_HARD_RESET_DETECT       (1 << 5)
-#define USBPD_REG_MASK_MSG_RX_DONE             (1 << 4)
-#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE (1 << 3)
-#define USBPD_REG_MASK_HARD_RESET_TX_DONE      (1 << 2)
-#define USBPD_REG_MASK_MSG_TX_DONE             (1 << 1)
-#define USBPD_REG_MASK_TIMER_TIMEOUT           (1 << 0)
+#define USBPD_REG_MASK_TYPE_C_DETECT           BIT(7)
+#define USBPD_REG_MASK_CABLE_RESET_DETECT      BIT(6)
+#define USBPD_REG_MASK_HARD_RESET_DETECT       BIT(5)
+#define USBPD_REG_MASK_MSG_RX_DONE             BIT(4)
+#define USBPD_REG_MASK_AUTO_SOFT_RESET_TX_DONE BIT(3)
+#define USBPD_REG_MASK_HARD_RESET_TX_DONE      BIT(2)
+#define USBPD_REG_MASK_MSG_TX_DONE             BIT(1)
+#define USBPD_REG_MASK_TIMER_TIMEOUT           BIT(0)
 #define IT83XX_USBPD_IMR(p)       REG8(IT83XX_USBPD_BASE(p)+0x15)
 #define IT83XX_USBPD_MTCR(p)      REG8(IT83XX_USBPD_BASE(p)+0x18)
-#define USBPD_REG_MASK_SW_RESET_TX_STAT        (1 << 3)
-#define USBPD_REG_MASK_TX_BUSY_STAT            (1 << 2)
-#define USBPD_REG_MASK_TX_DISCARD_STAT         (1 << 2)
-#define USBPD_REG_MASK_TX_ERR_STAT             (1 << 1)
-#define USBPD_REG_MASK_TX_START                (1 << 0)
+#define USBPD_REG_MASK_SW_RESET_TX_STAT        BIT(3)
+#define USBPD_REG_MASK_TX_BUSY_STAT            BIT(2)
+#define USBPD_REG_MASK_TX_DISCARD_STAT         BIT(2)
+#define USBPD_REG_MASK_TX_ERR_STAT             BIT(1)
+#define USBPD_REG_MASK_TX_START                BIT(0)
 #define IT83XX_USBPD_MTSR0(p)     REG8(IT83XX_USBPD_BASE(p)+0x19)
-#define USBPD_REG_MASK_CABLE_ENABLE            (1 << 7)
-#define USBPD_REG_MASK_SEND_HW_RESET           (1 << 6)
-#define USBPD_REG_MASK_SEND_BIST_MODE_2        (1 << 5)
+#define USBPD_REG_MASK_CABLE_ENABLE            BIT(7)
+#define USBPD_REG_MASK_SEND_HW_RESET           BIT(6)
+#define USBPD_REG_MASK_SEND_BIST_MODE_2        BIT(5)
 #define IT83XX_USBPD_MTSR1(p)     REG8(IT83XX_USBPD_BASE(p)+0x1A)
 #define IT83XX_USBPD_VDMMCSR(p)   REG8(IT83XX_USBPD_BASE(p)+0x1B)
 #define IT83XX_USBPD_MRSR(p)      REG8(IT83XX_USBPD_BASE(p)+0x1C)
-#define USBPD_REG_MASK_RX_MSG_VALID            (1 << 0)
+#define USBPD_REG_MASK_RX_MSG_VALID            BIT(0)
 #define IT83XX_USBPD_PEFSMR(p)    REG8(IT83XX_USBPD_BASE(p)+0x1D)
 #define IT83XX_USBPD_PES0R(p)     REG8(IT83XX_USBPD_BASE(p)+0x1E)
 #define IT83XX_USBPD_PES1R(p)     REG8(IT83XX_USBPD_BASE(p)+0x1F)
@@ -1252,11 +1252,11 @@ enum i2c_channels {
 #define IT83XX_USBPD_PDMHSR(p)    REG8(IT83XX_USBPD_BASE(p)+0x65)
 #ifdef IT83XX_INTC_PLUG_IN_SUPPORT
 #define IT83XX_USBPD_TCDCR(p)     REG8(IT83XX_USBPD_BASE(p)+0x67)
-#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT  (1 << 7)
-#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR   (1 << 4)
-#define USBPD_REG_PLUG_IN_OUT_SELECT           (1 << 3)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE   (1 << 1)
-#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT      (1 << 0)
+#define USBPD_REG_PLUG_OUT_DETECT_TYPE_SELECT  BIT(7)
+#define USBPD_REG_MASK_TYPEC_PLUG_IN_OUT_ISR   BIT(4)
+#define USBPD_REG_PLUG_IN_OUT_SELECT           BIT(3)
+#define USBPD_REG_PLUG_IN_OUT_DETECT_DISABLE   BIT(1)
+#define USBPD_REG_PLUG_IN_OUT_DETECT_STAT      BIT(0)
 #endif //IT83XX_INTC_PLUG_IN_SUPPORT
 
 enum usbpd_port {
@@ -1283,55 +1283,55 @@ enum usbpd_port {
 #define VW_VALID_FIELD(f)          ((f) << 4)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_2 0x2
-#define VW_IDX_2_SLP_S3            (1 << 0)
-#define VW_IDX_2_SLP_S4            (1 << 1)
-#define VW_IDX_2_SLP_S5            (1 << 2)
+#define VW_IDX_2_SLP_S3            BIT(0)
+#define VW_IDX_2_SLP_S4            BIT(1)
+#define VW_IDX_2_SLP_S5            BIT(2)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_3 0x3
-#define VW_IDX_3_SUS_STAT          (1 << 0)
-#define VW_IDX_3_PLTRST            (1 << 1)
-#define VW_IDX_3_OOB_RST_WARN      (1 << 2)
+#define VW_IDX_3_SUS_STAT          BIT(0)
+#define VW_IDX_3_PLTRST            BIT(1)
+#define VW_IDX_3_OOB_RST_WARN      BIT(2)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_4 0x4
-#define VW_IDX_4_OOB_RST_ACK       (1 << 0)
-#define VW_IDX_4_WAKE              (1 << 2)
-#define VW_IDX_4_PME               (1 << 3)
+#define VW_IDX_4_OOB_RST_ACK       BIT(0)
+#define VW_IDX_4_WAKE              BIT(2)
+#define VW_IDX_4_PME               BIT(3)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_5 0x5
-#define VW_IDX_5_SLAVE_BTLD_DONE   (1 << 0)
-#define VW_IDX_5_FATAL             (1 << 1)
-#define VW_IDX_5_NON_FATAL         (1 << 2)
-#define VW_IDX_5_SLAVE_BTLD_STATUS (1 << 3)
+#define VW_IDX_5_SLAVE_BTLD_DONE   BIT(0)
+#define VW_IDX_5_FATAL             BIT(1)
+#define VW_IDX_5_NON_FATAL         BIT(2)
+#define VW_IDX_5_SLAVE_BTLD_STATUS BIT(3)
 #define VW_IDX_5_BTLD_STATUS_DONE  (VW_IDX_5_SLAVE_BTLD_DONE | \
 					VW_IDX_5_SLAVE_BTLD_STATUS)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_6 0x6
-#define VW_IDX_6_SCI               (1 << 0)
-#define VW_IDX_6_SMI               (1 << 1)
-#define VW_IDX_6_RCIN              (1 << 2)
-#define VW_IDX_6_HOST_RST_ACK      (1 << 3)
+#define VW_IDX_6_SCI               BIT(0)
+#define VW_IDX_6_SMI               BIT(1)
+#define VW_IDX_6_RCIN              BIT(2)
+#define VW_IDX_6_HOST_RST_ACK      BIT(3)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_7 0x7
-#define VW_IDX_7_HOST_RST_WARN     (1 << 0)
+#define VW_IDX_7_HOST_RST_WARN     BIT(0)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_40 0x40
-#define VW_IDX_40_SUS_ACK           (1 << 0)
+#define VW_IDX_40_SUS_ACK           BIT(0)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_41 0x41
-#define VW_IDX_41_SUS_WARN          (1 << 0)
-#define VW_IDX_41_SUS_PWRDN_ACK     (1 << 1)
-#define VW_IDX_41_SLP_A             (1 << 3)
+#define VW_IDX_41_SUS_WARN          BIT(0)
+#define VW_IDX_41_SUS_PWRDN_ACK     BIT(1)
+#define VW_IDX_41_SLP_A             BIT(3)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_42 0x42
-#define VW_IDX_42_SLP_LAN           (1 << 0)
-#define VW_IDX_42_SLP_WLAN          (1 << 1)
+#define VW_IDX_42_SLP_LAN           BIT(0)
+#define VW_IDX_42_SLP_WLAN          BIT(1)
 
 #define ESPI_SYSTEM_EVENT_VW_IDX_43 0x43
 #define ESPI_SYSTEM_EVENT_VW_IDX_44 0x44
 #define ESPI_SYSTEM_EVENT_VW_IDX_47 0x47
 
 #define IT83XX_ESPI_VWCTRL0    REG8(IT83XX_ESPI_VW_BASE+0x90)
-#define ESPI_INTERRUPT_EVENT_PUT_PC (1 << 7)
+#define ESPI_INTERRUPT_EVENT_PUT_PC BIT(7)
 
 #define IT83XX_ESPI_VWCTRL1    REG8(IT83XX_ESPI_VW_BASE+0x91)
 #define IT83XX_ESPI_VWCTRL2    REG8(IT83XX_ESPI_VW_BASE+0x92)
@@ -1348,7 +1348,7 @@ enum usbpd_port {
 #define IT83XX_USB_BASE   0x00F02F00
 
 #define IT83XX_USB_P0MCR  REG8(IT83XX_USB_BASE+0xE4)
-#define USB_DP_DM_PULL_DOWN_EN (1 << 4)
+#define USB_DP_DM_PULL_DOWN_EN BIT(4)
 
 /* Wake pin definitions, defined at board-level */
 extern const enum gpio_signal hibernate_wake_pins[];
diff --git a/chip/it83xx/system.c b/chip/it83xx/system.c
index 98bf0e092a..d4f1987d4d 100644
--- a/chip/it83xx/system.c
+++ b/chip/it83xx/system.c
@@ -118,7 +118,7 @@ int system_is_reboot_warm(void)
 void chip_pre_init(void)
 {
 	/* bit4, enable debug mode through SMBus */
-	IT83XX_SMB_SLVISELR &= ~(1 << 4);
+	IT83XX_SMB_SLVISELR &= ~BIT(4);
 }
 
 #define BRAM_VALID_MAGIC        0x4252414D  /* "BRAM" */
@@ -189,12 +189,12 @@ void system_reset(int flags)
 	 * If we are in debug mode, we need disable it before triggering
 	 * a soft reset or reset will fail.
 	 */
-	IT83XX_SMB_SLVISELR |= (1 << 4);
+	IT83XX_SMB_SLVISELR |= BIT(4);
 
 	/* bit0: enable watchdog hardware reset. */
 #ifdef IT83XX_ETWD_HW_RESET_SUPPORT
 	if (flags & SYSTEM_RESET_HARD)
-		IT83XX_GCTRL_ETWDUARTCR |= (1 << 0);
+		IT83XX_GCTRL_ETWDUARTCR |= BIT(0);
 #endif
 	/*
 	 * Writing invalid key to watchdog module triggers a soft or hardware
diff --git a/chip/it83xx/uart.c b/chip/it83xx/uart.c
index 24dc2ec4c6..8cfbfdf466 100644
--- a/chip/it83xx/uart.c
+++ b/chip/it83xx/uart.c
@@ -209,10 +209,10 @@ void uart_init(void)
 	 * bit3: uart1 belongs to the EC side.
 	 * This is necessary for enabling eSPI module.
 	 */
-	IT83XX_GCTRL_RSTDMMC |= (1 << 3);
+	IT83XX_GCTRL_RSTDMMC |= BIT(3);
 
 	/* reset uart before config it */
-	IT83XX_GCTRL_RSTC4 |= (1 << 1);
+	IT83XX_GCTRL_RSTC4 |= BIT(1);
 
 	/* Waiting for when we can use the GPIO module to set pin muxing */
 	gpio_config_module(MODULE_UART, 1);
@@ -229,9 +229,9 @@ void uart_init(void)
 
 #ifdef CONFIG_UART_HOST
 	/* bit2, reset UART2 */
-	IT83XX_GCTRL_RSTC4 |= (1 << 2);
+	IT83XX_GCTRL_RSTC4 |= BIT(2);
 	/* SIN1/SOUT1 of UART 2 is enabled. */
-	IT83XX_GPIO_GRC1 |= (1 << 2);
+	IT83XX_GPIO_GRC1 |= BIT(2);
 	/* Config UART 2 */
 	host_uart_config();
 #endif
diff --git a/chip/it83xx/watchdog.c b/chip/it83xx/watchdog.c
index ee21170e34..c9641114ab 100644
--- a/chip/it83xx/watchdog.c
+++ b/chip/it83xx/watchdog.c
@@ -100,7 +100,7 @@ int watchdog_init(void)
 
 #ifdef CONFIG_HIBERNATE
 	/* bit4: watchdog can be stopped. */
-	IT83XX_ETWD_ETWCTRL |= (1 << 4);
+	IT83XX_ETWD_ETWCTRL |= BIT(4);
 #else
 	/* Specify that watchdog cannot be stopped. */
 	IT83XX_ETWD_ETWCTRL = 0x00;