diff options
| author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-10-16 16:06:19 +0800 |
|---|---|---|
| committer | Justin TerAvest <teravest@chromium.org> | 2020-10-16 19:25:37 +0000 |
| commit | a6b7fb3d3d1a185e5c89f7b086a1e80edf246109 (patch) | |
| tree | 28b043d9dbb3c3e05e8f7380f9b857321bb0c21c /chip/it83xx | |
| parent | 68fd8f49f6f3f37a5b62fdf5bd3226ee8a60aaa3 (diff) | |
| download | chrome-ec-a6b7fb3d3d1a185e5c89f7b086a1e80edf246109.tar.gz | |
it83xx/espi: re-enable port80 after espi reset
Our HW design is that Vcc on->off transition will disable port80.
Once we reset espi module, then Vcc has on -> off transition and
this cause port80 disabled. I re-enable port80 after espi reset.
BUG=b:163100497
BRANCH=none
TEST=On drawcia, check port80 values and SPCTRL1 register (= 0xc2)
after "reboot" and "power on" reset
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I2c6b0542cf08bee324e38886d1ce5909cd0b3776
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2479442
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'chip/it83xx')
| -rw-r--r-- | chip/it83xx/espi.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/chip/it83xx/espi.c b/chip/it83xx/espi.c index c731a7ad7e..8c81561712 100644 --- a/chip/it83xx/espi.c +++ b/chip/it83xx/espi.c @@ -438,6 +438,12 @@ void espi_reset_pin_asserted_interrupt(enum gpio_signal signal) { #ifdef IT83XX_ESPI_RESET_MODULE_BY_FW espi_fw_reset_module(); + /* + * bit[7], enable P80L function. + * bit[6], accept port 80h cycle. + * bit[1-0], 10b: I2EC is read-only. + */ + IT83XX_GCTRL_SPCTRL1 |= 0xC2; #endif /* reset vw_index_flag when espi_reset# asserted. */ espi_reset_vw_index_flags(); |