diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2020-11-30 11:06:38 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-12-17 03:23:42 +0000 |
| commit | de6289da947f23240b9234717799bb83250a2a72 (patch) | |
| tree | 1b6db85b4e8271873c065f517ad6a4247405dc47 /chip/it83xx | |
| parent | 3b1f01e3942b0fb8f07e9c113d79522a1f261815 (diff) | |
| download | chrome-ec-de6289da947f23240b9234717799bb83250a2a72.tar.gz | |
it83xx/flash: workaround of IMMU tag is nds32 only
This change excluded the workaround from core riscv.
BUG=b:111808417
BRANCH=none
TEST=On asurada and drawcia, no error while erasing and writing flash
of address 0x7e000 ~ 0x7f000
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: If6510b181173862684552607d688b3afb046aa2c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563356
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'chip/it83xx')
| -rw-r--r-- | chip/it83xx/flash.c | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c index df55ad77f4..6d3b9d8074 100644 --- a/chip/it83xx/flash.c +++ b/chip/it83xx/flash.c @@ -47,15 +47,14 @@ /* Read status register */ #define FLASH_CMD_RS 0x05 +#if (CONFIG_FLASH_SIZE == 0x80000) && defined(CHIP_CORE_NDS32) #define FLASH_TEXT_START ((uint32_t) &__flash_text_start) +/* Apply workaround of the issue (b:111808417) */ +#define IMMU_CACHE_TAG_INVALID /* The default tag index of immu. */ #define IMMU_TAG_INDEX_BY_DEFAULT 0x7E000 /* immu cache size is 8K bytes. */ #define IMMU_SIZE 0x2000 - -#if (CONFIG_FLASH_SIZE == 0x80000) && defined(CHIP_CORE_NDS32) -/* Apply workaround of the issue (b:111808417) */ -#define IMMU_CACHE_TAG_INVALID #endif static int stuck_locked; @@ -452,7 +451,11 @@ int FLASH_DMA_CODE flash_physical_write(int offset, int size, const char *data) interrupt_disable(); dma_flash_write(offset, size, data); +#ifdef IMMU_CACHE_TAG_INVALID dma_reset_immu((offset + size) >= IMMU_TAG_INDEX_BY_DEFAULT); +#else + dma_reset_immu(0); +#endif /* * Internal flash of N8 or RISC-V core is ILM(Instruction Local Memory) * mapped, but RISC-V's ILM base address is 0x80000000. @@ -515,7 +518,11 @@ int FLASH_DMA_CODE flash_physical_erase(int offset, int size) } #endif } +#ifdef IMMU_CACHE_TAG_INVALID dma_reset_immu((v_addr + v_size) >= IMMU_TAG_INDEX_BY_DEFAULT); +#else + dma_reset_immu(0); +#endif /* get the ILM address of a flash offset. */ v_addr |= CONFIG_MAPPED_STORAGE_BASE; ret = dma_flash_verify(v_addr, v_size, NULL); |