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| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2018-03-22 04:55:51 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-24 07:32:29 -0700 |
| commit | 3bd4e0de5edc6f62eda8739d31816b5b29d1979b (patch) | |
| tree | d6cc7049652e5fc41b765e0708e8722e4ca7bd24 /chip/it83xx | |
| parent | f59290878e5fcd99add71aec74baea7d1e3f0297 (diff) | |
| download | chrome-ec-3bd4e0de5edc6f62eda8739d31816b5b29d1979b.tar.gz | |
Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_L
Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel
chipset variants have same GPIO name for doing SOC internal reset.
BUG=b:72426192
BRANCH=none
TEST=make buildall -j
Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/974241
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'chip/it83xx')
| -rw-r--r-- | chip/it83xx/lpc.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/chip/it83xx/lpc.c b/chip/it83xx/lpc.c index 8fd08f2b90..231dd25ece 100644 --- a/chip/it83xx/lpc.c +++ b/chip/it83xx/lpc.c @@ -711,9 +711,9 @@ void lpc_host_reset(void) udelay(10); espi_vw_set_wire(VW_RCIN_L, 1); #else - gpio_set_level(GPIO_PCH_RCIN_L, 0); + gpio_set_level(GPIO_SYS_RESET_L, 0); udelay(10); - gpio_set_level(GPIO_PCH_RCIN_L, 1); + gpio_set_level(GPIO_SYS_RESET_L, 1); #endif } |