cleanup: Combined i2c unwedge code into one common function

Refactored the i2c unwedge code to place it in the common directory
so that any EC chip can use it.

Added to the STM32F and LM4 boards, code to automatically detect and
unwedge the i2c bus at the start of an i2c transaction. Note that STM32L
already had this ability.

To enable unwedging of the i2c port though, the gpio pins for SDA and
SCL must be defined in the i2c_ports[] array in the board.c file. This
allows the i2c module to bit bang the unwedging for the given port. If
SDA and SCL are not defined for the port, then the unwedge code will
not run.

BUG=chrome-os-partner:26315, chrome-os-partner:23802
BRANCH=none
TEST=Manual testing on machines with different EC chips.

Testing made extensive use of https://chromium-review.googlesource.com/66389
in order to force wedging of the i2c bus so that we can attempt to unwedge
it. Note that you can easily test if the bus is wedged by running i2cscan.

On pit and spring:
On pit, after each of the following, I verified that the bus was automatically
unwedged.
On spring, the unwedge only runs at reboot, so, for the non-reboot wedge
commands, I manually ran console command unwedge, and verified that the bus
became unwedged.
(1) Bit bang a transaction but only read part of the response.
    Command to wedge: i2cwedge 0x90 0 2 2
(2) Bit bang a transaction to do a "write" and stop while the other side is
    acking. Command to wedge: i2cwedge 0x90 0 1
(3) Same as (1) but do a reboot instead of returning and see
    that the unwedge works at init time w/ no cancelled transactions.
    Command to wedge: i2cwedge 0x90 0 6 2
(4) Same as (2) but do a reboot instead of returning and see
    that the unwedge works at init time w/ no cancelled transactions.
    Command to wedge: i2cwedge 0x90 0 5

On glimmer:
Added code to call i2c_unwedge in accel_init(). Then tested unwedging the
accelerometer with the following. One extra difficulty testing this with
the accelerometer is that sometimes the bit you stop on is high, which
means it won't be wedged at all, the next start transaction will reset
the bus. So, sometimes running i2cwedge won't wedge the bus and sometimes
it will depending on the acceleration data.
(1) Big bang transaction to do a "read" of accelerometer and stop partway:
    i2cwedge 0x1c 0x0f 2 2
    i2cscan to make sure bus is actually wedged
    i2cunwedge
    i2cscan to make sure bus is now unwedged.
(2) Bit bang transaction to do a "read" and stop partway, then reboot:
    i2cwedge 0x1c 0x0f 6 2.
    i2cscan to verify that the bus is working after the reboot.

Change-Id: Ie3328e843ffb40f5001c96626fea131c0f9ad9b1
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188422
Reviewed-by: Randall Spangler <rspangler@chromium.org>

1 files changed, 63 insertions, 8 deletions

diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c
index 510b8aaa1d..e888b31361 100644
--- a/chip/lm4/i2c.c
+++ b/chip/lm4/i2c.c
@@ -161,12 +161,6 @@ int i2c_do_work(int port)
 	return 0;
 }
 
-int i2c_get_line_levels(int port)
-{
-	/* Conveniently, MBMON bit (1 << 1) is SDA and (1 << 0) is SCL. */
-	return LM4_I2C_MBMON(port) & 0x03;
-}
-
 int i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_size,
 	     uint8_t *in, int in_size, int flags)
 {
@@ -189,10 +183,17 @@ int i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_size,
 
 	/* Make sure we're in a good state to start */
 	if ((flags & I2C_XFER_START) &&
-	    (reg_mcs & (LM4_I2C_MCS_CLKTO | LM4_I2C_MCS_ARBLST))) {
+	    ((reg_mcs & (LM4_I2C_MCS_CLKTO | LM4_I2C_MCS_ARBLST)) ||
+			    (i2c_get_line_levels(port) != I2C_LINE_IDLE))) {
 		uint32_t tpr = LM4_I2C_MTPR(port);
 
-		CPRINTF("[%T I2C%d bad status 0x%02x]\n", port, reg_mcs);
+		CPRINTF("[%T I2C%d bad status 0x%02x, SCL=%d, SDA=%d]\n", port,
+				reg_mcs,
+				i2c_get_line_levels(port) & I2C_LINE_SCL_HIGH,
+				i2c_get_line_levels(port) & I2C_LINE_SDA_HIGH);
+
+		/* Attempt to unwedge the port. */
+		i2c_unwedge(port);
 
 		/* Clock timeout or arbitration lost.  Reset port to clear. */
 		LM4_SYSTEM_SRI2C |= (1 << port);
@@ -265,6 +266,60 @@ int i2c_xfer(int port, int slave_addr, const uint8_t *out, int out_size,
 	return pd->err;
 }
 
+int i2c_raw_get_scl(int port)
+{
+	enum gpio_signal g;
+	int ret;
+
+	/* If no SCL pin defined for this port, then return 1 to appear idle. */
+	if (get_scl_from_i2c_port(port, &g) != EC_SUCCESS)
+		return 1;
+
+	/* If we are driving the pin low, it must be low. */
+	if (gpio_get_level(g) == 0)
+		return 0;
+
+	/*
+	 * Otherwise, we need to toggle it to an input to read the true pin
+	 * state.
+	 */
+	gpio_set_flags(g, GPIO_INPUT);
+	ret = gpio_get_level(g);
+	gpio_set_flags(g, GPIO_ODR_HIGH);
+
+	return ret;
+}
+
+int i2c_raw_get_sda(int port)
+{
+	enum gpio_signal g;
+	int ret;
+
+	/* If no SDA pin defined for this port, then return 1 to appear idle. */
+	if (get_sda_from_i2c_port(port, &g) != EC_SUCCESS)
+		return 1;
+
+	/* If we are driving the pin low, it must be low. */
+	if (gpio_get_level(g) == 0)
+		return 0;
+
+	/*
+	 * Otherwise, we need to toggle it to an input to read the true pin
+	 * state.
+	 */
+	gpio_set_flags(g, GPIO_INPUT);
+	ret = gpio_get_level(g);
+	gpio_set_flags(g, GPIO_ODR_HIGH);
+
+	return ret;
+}
+
+int i2c_get_line_levels(int port)
+{
+	/* Conveniently, MBMON bit (1 << 1) is SDA and (1 << 0) is SCL. */
+	return LM4_I2C_MBMON(port) & 0x03;
+}
+
 int i2c_read_string(int port, int slave_addr, int offset, uint8_t *data,
 		    int len)
 {