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| author | Randall Spangler <rspangler@chromium.org> | 2013-12-17 13:43:17 -0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2013-12-19 00:12:28 +0000 |
| commit | 6ab8e91658f1efc894b648cc0748af8d804915e4 (patch) | |
| tree | c33da7914793452ecb37084e505230171d4eff9e /chip/lm4/spi.c | |
| parent | e5935f17d1798a1f19c6003e57f140446774484f (diff) | |
| download | chrome-ec-6ab8e91658f1efc894b648cc0748af8d804915e4.tar.gz | |
cleanup: Remove checkpatch warnings
This make minor syntactic changes and renames some camel-cased symbols
to keep checkpatch from complaining. The goal is to reduce the
temptation to use 'repo upload --no-verify'.
This is a big furball of find/replace, but no functional changes.
BUG=chromium:322144
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180495
Diffstat (limited to 'chip/lm4/spi.c')
| -rw-r--r-- | chip/lm4/spi.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/chip/lm4/spi.c b/chip/lm4/spi.c index 914e5f1c66..aa8785ed0e 100644 --- a/chip/lm4/spi.c +++ b/chip/lm4/spi.c @@ -25,8 +25,8 @@ int spi_enable(int enable) gpio_config_module(MODULE_SPI, 1); /* Don't use the SSI0 frame output. CS# is a GPIO so we can * keep it low during an entire transaction. */ - gpio_set_flags(GPIO_SPI_CSn, GPIO_OUTPUT); - gpio_set_level(GPIO_SPI_CSn, 1); + gpio_set_flags(GPIO_SPI_CS_L, GPIO_OUTPUT); + gpio_set_level(GPIO_SPI_CS_L, 1); /* Enable SSI port */ LM4_SSI_CR1(0) |= 0x02; @@ -35,8 +35,8 @@ int spi_enable(int enable) LM4_SSI_CR1(0) &= ~0x02; /* Make sure CS# is deselected */ - gpio_set_level(GPIO_SPI_CSn, 1); - gpio_set_flags(GPIO_SPI_CSn, GPIO_ODR_HIGH); + gpio_set_level(GPIO_SPI_CS_L, 1); + gpio_set_flags(GPIO_SPI_CS_L, GPIO_ODR_HIGH); gpio_config_module(MODULE_SPI, 0); } @@ -59,7 +59,7 @@ int spi_transaction(const uint8_t *txdata, int txlen, /* Start transaction. Need to do this explicitly because the LM4 * SSI controller pulses its frame select every byte, and the EEPROM * wants the chip select held low during the entire transaction. */ - gpio_set_level(GPIO_SPI_CSn, 0); + gpio_set_level(GPIO_SPI_CS_L, 0); while (rxcount < totallen) { /* Handle received bytes if any. We just checked rxcount < @@ -89,7 +89,7 @@ int spi_transaction(const uint8_t *txdata, int txlen, } /* End transaction */ - gpio_set_level(GPIO_SPI_CSn, 1); + gpio_set_level(GPIO_SPI_CS_L, 1); return EC_SUCCESS; } |