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authorChromeOS Developer <dparker@chromium.org>2013-12-11 14:40:30 -0800
committerchrome-internal-fetch <chrome-internal-fetch@google.com>2013-12-13 01:13:38 +0000
commitdf50fccf8e87bbf0328e58bd012b577bd4c7658a (patch)
treeae378c378bf14e4e12d0ddb0cefb52221969e5d7 /chip/lm4
parentebb8c88a5991333606900a4234ecafc402b5d2b7 (diff)
downloadchrome-ec-df50fccf8e87bbf0328e58bd012b577bd4c7658a.tar.gz
Change PECI_TJMAX to a board config option
BUG=chrome-os-partner:24455 BRANCH=none TEST=Manual: Verify that CONIFG_PECI_TJMAX set per-board matches the value queried over the PECI bus with the restricted "peciprobe" command. Change-Id: I8e99a23a66f26d6101e01cc751d0a8ca79686321 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179682 Reviewed-by: Alec Berg <alecaberg@chromium.org>
Diffstat (limited to 'chip/lm4')
-rw-r--r--chip/lm4/peci.c17
1 files changed, 4 insertions, 13 deletions
diff --git a/chip/lm4/peci.c b/chip/lm4/peci.c
index d66956202b..052e2ddc06 100644
--- a/chip/lm4/peci.c
+++ b/chip/lm4/peci.c
@@ -16,15 +16,6 @@
#include "temp_sensor.h"
#include "util.h"
-/*
- * Max junction temperature for processor in degrees C. This is correct for
- * Ivy Bridge and Haswell; future chips don't have PECI.
- *
- * In theory we could read TjMax from the processor via PECI, but that requires
- * closed-source Intel PECI commands.
- */
-#define PECI_TJMAX 105
-
/* Initial PECI baud rate */
#define PECI_BAUD_RATE 100000
@@ -79,9 +70,9 @@ int peci_temp_sensor_get_val(int idx, int *temp_ptr)
* Require at least two valid samples. When the AP transitions into S0,
* it is possible, depending on the timing of the PECI sample, to read
* an invalid temperature. This is very rare, but when it does happen
- * the temperature returned is PECI_TJMAX. Requiring two valid samples
- * here assures us that one bad maximum temperature reading when
- * entering S0 won't cause us to trigger an over temperature.
+ * the temperature returned is CONFIG_PECI_TJMAX. Requiring two valid
+ * samples here assures us that one bad maximum temperature reading
+ * when entering S0 won't cause us to trigger an over temperature.
*/
if (success_cnt < 2)
return EC_ERROR_UNKNOWN;
@@ -117,7 +108,7 @@ static void peci_freq_changed(void)
(PECI_POLL_INTERVAL_MS * (freq / 1000 / 4096));
/* Set up temperature monitoring to report in degrees K */
- LM4_PECI_CTL = ((PECI_TJMAX + 273) << 22) | 0x0001 |
+ LM4_PECI_CTL = ((CONFIG_PECI_TJMAX + 273) << 22) | 0x0001 |
(PECI_RETRY_COUNT << 12) |
(PECI_ERROR_BYPASS << 11);
}