force the compiler to use a valid register allocation for irq handlers

When we are calling the re-scheduling routine at the end of an irq
handling routine, we need to ensure that the high registers are not
currently saved on the system stack.
On Cortex-M3/M4, the compiler is normally doing tail-call optimization
there and behaving properly, but this fixes the fact that insanely large
interrupt handling routines where sometimes not compile and not running
properly (aka issue 24515).

This also prepares for one more core-specific DECLARE_IRQ routine on
Cortex-M0.

Note: now on, the IRQ handling routines should no longer be "static".

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=chrome-os-partner:24515
TEST=make -j buildall
revert the workaround for 24515, see the issue happening only without
this CL.

Change-Id: Ic419369231925568df05815fd079ed191a5446db
Reviewed-on: https://chromium-review.googlesource.com/189153
Reviewed-by: Vic Yang <victoryang@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>

8 files changed, 17 insertions, 18 deletions

diff --git a/chip/lm4/adc.c b/chip/lm4/adc.c
index 19548b12bd..e58945605e 100644
--- a/chip/lm4/adc.c
+++ b/chip/lm4/adc.c
@@ -192,10 +192,10 @@ static void handle_interrupt(int ss)
 		task_wake(id);
 }
 
-static void ss0_interrupt(void) { handle_interrupt(0); }
-static void ss1_interrupt(void) { handle_interrupt(1); }
-static void ss2_interrupt(void) { handle_interrupt(2); }
-static void ss3_interrupt(void) { handle_interrupt(3); }
+void ss0_interrupt(void) { handle_interrupt(0); }
+void ss1_interrupt(void) { handle_interrupt(1); }
+void ss2_interrupt(void) { handle_interrupt(2); }
+void ss3_interrupt(void) { handle_interrupt(3); }
 
 DECLARE_IRQ(LM4_IRQ_ADC0_SS0, ss0_interrupt, 2);
 DECLARE_IRQ(LM4_IRQ_ADC0_SS1, ss1_interrupt, 2);
diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c
index 58d7665f20..e5236e31d2 100644
--- a/chip/lm4/gpio.c
+++ b/chip/lm4/gpio.c
@@ -318,7 +318,7 @@ static void gpio_interrupt(int port, uint32_t mis)
  * the port, then call the master handler above.
  */
 #define GPIO_IRQ_FUNC(irqfunc, gpiobase)		\
-	static void irqfunc(void)			\
+	void irqfunc(void)				\
 	{						\
 		uint32_t mis = LM4_GPIO_MIS(gpiobase);	\
 		LM4_GPIO_ICR(gpiobase) = mis;		\
diff --git a/chip/lm4/hwtimer.c b/chip/lm4/hwtimer.c
index 088bd5713b..17d9c3e6ea 100644
--- a/chip/lm4/hwtimer.c
+++ b/chip/lm4/hwtimer.c
@@ -42,7 +42,7 @@ void __hw_clock_source_set(uint32_t ts)
 	LM4_TIMER_TAV(6) = 0xffffffff - ts;
 }
 
-static void __hw_clock_source_irq(void)
+void __hw_clock_source_irq(void)
 {
 	uint32_t status = LM4_TIMER_RIS(6);
 
diff --git a/chip/lm4/i2c.c b/chip/lm4/i2c.c
index e888b31361..f50296678b 100644
--- a/chip/lm4/i2c.c
+++ b/chip/lm4/i2c.c
@@ -436,12 +436,12 @@ static void handle_interrupt(int port)
 		task_set_event(id, TASK_EVENT_I2C_IDLE, 0);
 }
 
-static void i2c0_interrupt(void) { handle_interrupt(0); }
-static void i2c1_interrupt(void) { handle_interrupt(1); }
-static void i2c2_interrupt(void) { handle_interrupt(2); }
-static void i2c3_interrupt(void) { handle_interrupt(3); }
-static void i2c4_interrupt(void) { handle_interrupt(4); }
-static void i2c5_interrupt(void) { handle_interrupt(5); }
+void i2c0_interrupt(void) { handle_interrupt(0); }
+void i2c1_interrupt(void) { handle_interrupt(1); }
+void i2c2_interrupt(void) { handle_interrupt(2); }
+void i2c3_interrupt(void) { handle_interrupt(3); }
+void i2c4_interrupt(void) { handle_interrupt(4); }
+void i2c5_interrupt(void) { handle_interrupt(5); }
 
 DECLARE_IRQ(LM4_IRQ_I2C0, i2c0_interrupt, 2);
 DECLARE_IRQ(LM4_IRQ_I2C1, i2c1_interrupt, 2);
diff --git a/chip/lm4/keyboard_raw.c b/chip/lm4/keyboard_raw.c
index 06f592b64c..66d66de1fa 100644
--- a/chip/lm4/keyboard_raw.c
+++ b/chip/lm4/keyboard_raw.c
@@ -108,7 +108,7 @@ void keyboard_raw_enable_interrupt(int enable)
 /**
  * Interrupt handler for the entire GPIO bank of keyboard rows.
  */
-static void keyboard_raw_interrupt(void)
+void keyboard_raw_interrupt(void)
 {
 	/* Clear all pending keyboard interrupts */
 	LM4_GPIO_ICR(KB_SCAN_ROW_GPIO) = 0xff;
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index aa15e1fbfe..f2fd650016 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -401,7 +401,6 @@ uint32_t lpc_get_host_event_mask(enum lpc_host_event_type type)
  *
  * @param is_cmd	Is write command (is_cmd=1) or data (is_cmd=0)
  */
-__attribute__((noinline))			/* TODO(crosbug.com/p/24515) */
 static void handle_acpi_write(int is_cmd)
 {
 	uint8_t value, result;
@@ -520,7 +519,7 @@ static void handle_host_write(int is_cmd)
 /**
  * LPC interrupt handler
  */
-static void lpc_interrupt(void)
+void lpc_interrupt(void)
 {
 	uint32_t mis = LM4_LPC_LPCMIS;
 	uint32_t st;
diff --git a/chip/lm4/system.c b/chip/lm4/system.c
index 0741d0c7f3..6a55b2941e 100644
--- a/chip/lm4/system.c
+++ b/chip/lm4/system.c
@@ -316,7 +316,7 @@ void system_reset_rtc_alarm(void)
 /**
  * Hibernate module interrupt
  */
-static void __hibernate_irq(void)
+void __hibernate_irq(void)
 {
 	system_reset_rtc_alarm();
 }
diff --git a/chip/lm4/uart.c b/chip/lm4/uart.c
index 95c9bdba32..befe0ec398 100644
--- a/chip/lm4/uart.c
+++ b/chip/lm4/uart.c
@@ -111,7 +111,7 @@ void uart_enable_interrupt(void)
 /**
  * Interrupt handler for UART0
  */
-static void uart_ec_interrupt(void)
+void uart_ec_interrupt(void)
 {
 	/* Clear transmit and receive interrupt status */
 	LM4_UART_ICR(0) = 0x70;
@@ -128,7 +128,7 @@ DECLARE_IRQ(LM4_IRQ_UART0, uart_ec_interrupt, 1);
 /**
  * Interrupt handler for Host UART
  */
-static void uart_host_interrupt(void)
+void uart_host_interrupt(void)
 {
 	/* Clear transmit and receive interrupt status */
 	LM4_UART_ICR(CONFIG_UART_HOST) = 0x70;