diff options
author | Tom Hughes <tomhughes@chromium.org> | 2022-09-21 14:10:01 -0700 |
---|---|---|
committer | Tom Hughes <tomhughes@chromium.org> | 2022-09-22 12:49:33 -0700 |
commit | 2bcf863b492fe7ed8105c853814dba6ed32ba719 (patch) | |
tree | fcf6ce5810f9ff9e3c8cce434812dd75492269ed /chip/max32660/gpio_regs.h | |
parent | e5fb0b9ba488614b5684e640530f00821ab7b943 (diff) | |
parent | 28712dae9d7ed1e694f7622cc083afa71090d4d5 (diff) | |
download | chrome-ec-2bcf863b492fe7ed8105c853814dba6ed32ba719.tar.gz |
Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-releasefirmware-fpmcu-bloonchipper-release
Generated by: ./util/update_release_branch.py --board bloonchipper
--relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware-
fpmcu-bloonchipper-release
Relevant changes:
git log --oneline e5fb0b9ba4..28712dae9d -- board/hatch_fp
board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh
ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dc3e9008b8 board/hatch_fp/board.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header
BRANCH=None
BUG=b:246424843 b:234181908 b:244781166 b:234181908 b:244387210
BUG=b:242720240 chromium:1098010 b:180945056 b:236025198 b:234181908
BUG=b:234181908 b:237344361 b:131913998 b:236386294 b:234143158
BUG=b:234781655 b:215613183 b:242720910
TEST=`make -j buildall`
TEST=./test/run_device_tests.py --board bloonchipper
Test "aes": PASSED
Test "cec": PASSED
Test "cortexm_fpu": PASSED
Test "crc": PASSED
Test "flash_physical": PASSED
Test "flash_write_protect": PASSED
Test "fpsensor_hw": PASSED
Test "fpsensor_spi_ro": PASSED
Test "fpsensor_spi_rw": PASSED
Test "fpsensor_uart_ro": PASSED
Test "fpsensor_uart_rw": PASSED
Test "mpu_ro": PASSED
Test "mpu_rw": PASSED
Test "mutex": PASSED
Test "pingpong": PASSED
Test "printf": PASSED
Test "queue": PASSED
Test "rollback_region0": PASSED
Test "rollback_region1": PASSED
Test "rollback_entropy": PASSED
Test "rtc": PASSED
Test "sha256": PASSED
Test "sha256_unrolled": PASSED
Test "static_if": PASSED
Test "stdlib": PASSED
Test "system_is_locked_wp_on": PASSED
Test "system_is_locked_wp_off": PASSED
Test "timer_dos": PASSED
Test "utils": PASSED
Test "utils_str": PASSED
Test "stm32f_rtc": PASSED
Test "panic_data_bloonchipper_v2.0.4277": PASSED
Test "panic_data_bloonchipper_v2.0.5938": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I264ad0ffe7afcd507a1e483c6e934a9c4fea47c3
Diffstat (limited to 'chip/max32660/gpio_regs.h')
-rw-r--r-- | chip/max32660/gpio_regs.h | 721 |
1 files changed, 375 insertions, 346 deletions
diff --git a/chip/max32660/gpio_regs.h b/chip/max32660/gpio_regs.h index 1c6fcf7a71..70b706b2c0 100644 --- a/chip/max32660/gpio_regs.h +++ b/chip/max32660/gpio_regs.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -40,65 +40,65 @@ * Structure type to access the GPIO Registers. */ typedef struct { - __IO uint32_t en; /**< <tt>\b 0x00:<\tt> GPIO EN Register */ + __IO uint32_t en; /**< <tt>\b 0x00:<\tt> GPIO EN Register */ __IO uint32_t en_set; /**< <tt>\b 0x04:<\tt> GPIO EN_SET Register */ __IO uint32_t en_clr; /**< <tt>\b 0x08:<\tt> GPIO EN_CLR Register */ __IO uint32_t out_en; /**< <tt>\b 0x0C:<\tt> GPIO OUT_EN Register */ - __IO uint32_t - out_en_set; /**< <tt>\b 0x10:<\tt> GPIO OUT_EN_SET Register */ - __IO uint32_t - out_en_clr; /**< <tt>\b 0x14:<\tt> GPIO OUT_EN_CLR Register */ - __IO uint32_t out; /**< <tt>\b 0x18:<\tt> GPIO OUT Register */ + __IO uint32_t out_en_set; /**< <tt>\b 0x10:<\tt> GPIO OUT_EN_SET + Register */ + __IO uint32_t out_en_clr; /**< <tt>\b 0x14:<\tt> GPIO OUT_EN_CLR + Register */ + __IO uint32_t out; /**< <tt>\b 0x18:<\tt> GPIO OUT Register */ __O uint32_t out_set; /**< <tt>\b 0x1C:<\tt> GPIO OUT_SET Register */ __O uint32_t out_clr; /**< <tt>\b 0x20:<\tt> GPIO OUT_CLR Register */ - __I uint32_t in; /**< <tt>\b 0x24:<\tt> GPIO IN Register */ + __I uint32_t in; /**< <tt>\b 0x24:<\tt> GPIO IN Register */ __IO uint32_t int_mod; /**< <tt>\b 0x28:<\tt> GPIO INT_MOD Register */ __IO uint32_t int_pol; /**< <tt>\b 0x2C:<\tt> GPIO INT_POL Register */ __R uint32_t rsv_0x30; __IO uint32_t int_en; /**< <tt>\b 0x34:<\tt> GPIO INT_EN Register */ - __IO uint32_t - int_en_set; /**< <tt>\b 0x38:<\tt> GPIO INT_EN_SET Register */ - __IO uint32_t - int_en_clr; /**< <tt>\b 0x3C:<\tt> GPIO INT_EN_CLR Register */ + __IO uint32_t int_en_set; /**< <tt>\b 0x38:<\tt> GPIO INT_EN_SET + Register */ + __IO uint32_t int_en_clr; /**< <tt>\b 0x3C:<\tt> GPIO INT_EN_CLR + Register */ __I uint32_t int_stat; /**< <tt>\b 0x40:<\tt> GPIO INT_STAT Register */ __R uint32_t rsv_0x44; __IO uint32_t int_clr; /**< <tt>\b 0x48:<\tt> GPIO INT_CLR Register */ __IO uint32_t wake_en; /**< <tt>\b 0x4C:<\tt> GPIO WAKE_EN Register */ - __IO uint32_t - wake_en_set; /**< <tt>\b 0x50:<\tt> GPIO WAKE_EN_SET Register */ - __IO uint32_t - wake_en_clr; /**< <tt>\b 0x54:<\tt> GPIO WAKE_EN_CLR Register */ + __IO uint32_t wake_en_set; /**< <tt>\b 0x50:<\tt> GPIO WAKE_EN_SET + Register */ + __IO uint32_t wake_en_clr; /**< <tt>\b 0x54:<\tt> GPIO WAKE_EN_CLR + Register */ __R uint32_t rsv_0x58; __IO uint32_t int_dual_edge; /**< <tt>\b 0x5C:<\tt> GPIO INT_DUAL_EDGE Register */ __IO uint32_t pad_cfg1; /**< <tt>\b 0x60:<\tt> GPIO PAD_CFG1 Register */ __IO uint32_t pad_cfg2; /**< <tt>\b 0x64:<\tt> GPIO PAD_CFG2 Register */ - __IO uint32_t en1; /**< <tt>\b 0x68:<\tt> GPIO EN1 Register */ - __IO uint32_t en1_set; /**< <tt>\b 0x6C:<\tt> GPIO EN1_SET Register */ - __IO uint32_t en1_clr; /**< <tt>\b 0x70:<\tt> GPIO EN1_CLR Register */ - __IO uint32_t en2; /**< <tt>\b 0x74:<\tt> GPIO EN2 Register */ - __IO uint32_t en2_set; /**< <tt>\b 0x78:<\tt> GPIO EN2_SET Register */ - __IO uint32_t en2_clr; /**< <tt>\b 0x7C:<\tt> GPIO EN2_CLR Register */ + __IO uint32_t en1; /**< <tt>\b 0x68:<\tt> GPIO EN1 Register */ + __IO uint32_t en1_set; /**< <tt>\b 0x6C:<\tt> GPIO EN1_SET Register */ + __IO uint32_t en1_clr; /**< <tt>\b 0x70:<\tt> GPIO EN1_CLR Register */ + __IO uint32_t en2; /**< <tt>\b 0x74:<\tt> GPIO EN2 Register */ + __IO uint32_t en2_set; /**< <tt>\b 0x78:<\tt> GPIO EN2_SET Register */ + __IO uint32_t en2_clr; /**< <tt>\b 0x7C:<\tt> GPIO EN2_CLR Register */ __R uint32_t rsv_0x80_0xa7[10]; - __IO uint32_t is; /**< <tt>\b 0xA8:<\tt> GPIO IS Register */ - __IO uint32_t sr; /**< <tt>\b 0xAC:<\tt> GPIO SR Register */ - __IO uint32_t ds; /**< <tt>\b 0xB0:<\tt> GPIO DS Register */ + __IO uint32_t is; /**< <tt>\b 0xA8:<\tt> GPIO IS Register */ + __IO uint32_t sr; /**< <tt>\b 0xAC:<\tt> GPIO SR Register */ + __IO uint32_t ds; /**< <tt>\b 0xB0:<\tt> GPIO DS Register */ __IO uint32_t ds1; /**< <tt>\b 0xB4:<\tt> GPIO DS1 Register */ - __IO uint32_t ps; /**< <tt>\b 0xB8:<\tt> GPIO PS Register */ + __IO uint32_t ps; /**< <tt>\b 0xB8:<\tt> GPIO PS Register */ __R uint32_t rsv_0xbc; __IO uint32_t vssel; /**< <tt>\b 0xC0:<\tt> GPIO VSSEL Register */ } mxc_gpio_regs_t; -#define PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */ -#define PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */ -#define PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */ -#define PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */ -#define PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */ -#define PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */ -#define PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */ -#define PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */ -#define PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */ -#define PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */ +#define PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */ +#define PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */ +#define PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */ +#define PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */ +#define PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */ +#define PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */ +#define PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */ +#define PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */ +#define PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */ +#define PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */ #define PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */ #define PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */ #define PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */ @@ -126,8 +126,8 @@ typedef struct { * Enumeration type for the GPIO Function Type */ typedef enum { - GPIO_FUNC_IN, /**< GPIO Input */ - GPIO_FUNC_OUT, /**< GPIO Output */ + GPIO_FUNC_IN, /**< GPIO Input */ + GPIO_FUNC_OUT, /**< GPIO Output */ GPIO_FUNC_ALT1, /**< Alternate Function Selection */ GPIO_FUNC_ALT2, /**< Alternate Function Selection */ GPIO_FUNC_ALT3, /**< Alternate Function Selection */ @@ -138,8 +138,8 @@ typedef enum { * Enumeration type for the type of GPIO pad on a given pin. */ typedef enum { - GPIO_PAD_NONE, /**< No pull-up or pull-down */ - GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */ + GPIO_PAD_NONE, /**< No pull-up or pull-down */ + GPIO_PAD_PULL_UP, /**< Set pad to weak pull-up */ GPIO_PAD_PULL_DOWN, /**< Set pad to weak pull-down */ } gpio_pad_t; @@ -147,10 +147,10 @@ typedef enum { * Structure type for configuring a GPIO port. */ typedef struct { - uint32_t port; /**< Index of GPIO port */ - uint32_t mask; /**< Pin mask (multiple pins may be set) */ + uint32_t port; /**< Index of GPIO port */ + uint32_t mask; /**< Pin mask (multiple pins may be set) */ gpio_func_t func; /**< Function type */ - gpio_pad_t pad; /**< Pad type */ + gpio_pad_t pad; /**< Pad type */ } gpio_cfg_t; typedef enum { GPIO_INTERRUPT_LEVEL, GPIO_INTERRUPT_EDGE } gpio_int_mode_t; @@ -166,110 +166,110 @@ typedef enum { } gpio_int_pol_t; /* Register offsets for module GPIO */ -#define MXC_R_GPIO_EN \ - ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_EN \ + ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x000 */ -#define MXC_R_GPIO_EN_SET \ - ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_EN_SET \ + ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x004 */ -#define MXC_R_GPIO_EN_CLR \ - ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_EN_CLR \ + ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x008 */ -#define MXC_R_GPIO_OUT_EN \ - ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_OUT_EN \ + ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: <tt> \ 0x0x00C */ -#define MXC_R_GPIO_OUT_EN_SET \ - ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_OUT_EN_SET \ + ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x010 */ -#define MXC_R_GPIO_OUT_EN_CLR \ - ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_OUT_EN_CLR \ + ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x014 */ -#define MXC_R_GPIO_OUT \ - ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_OUT \ + ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x018 */ -#define MXC_R_GPIO_OUT_SET \ - ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_OUT_SET \ + ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: <tt> \ 0x0x01C */ -#define MXC_R_GPIO_OUT_CLR \ - ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_OUT_CLR \ + ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x020 */ -#define MXC_R_GPIO_IN \ - ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_IN \ + ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x024 */ -#define MXC_R_GPIO_INT_MOD \ - ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_INT_MOD \ + ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x028 */ -#define MXC_R_GPIO_INT_POL \ - ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_INT_POL \ + ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> \ 0x0x02C */ -#define MXC_R_GPIO_INT_EN \ - ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_INT_EN \ + ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x034 */ -#define MXC_R_GPIO_INT_EN_SET \ - ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_INT_EN_SET \ + ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x038 */ -#define MXC_R_GPIO_INT_EN_CLR \ - ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_INT_EN_CLR \ + ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> \ 0x0x03C */ -#define MXC_R_GPIO_INT_STAT \ - ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_INT_STAT \ + ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x040 */ -#define MXC_R_GPIO_INT_CLR \ - ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_INT_CLR \ + ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x048 */ -#define MXC_R_GPIO_WAKE_EN \ - ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_WAKE_EN \ + ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: <tt> \ 0x0x04C */ -#define MXC_R_GPIO_WAKE_EN_SET \ - ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_WAKE_EN_SET \ + ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x050 */ -#define MXC_R_GPIO_WAKE_EN_CLR \ - ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_WAKE_EN_CLR \ + ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x054 */ -#define MXC_R_GPIO_INT_DUAL_EDGE \ - ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_INT_DUAL_EDGE \ + ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: <tt> \ 0x0x05C */ -#define MXC_R_GPIO_PAD_CFG1 \ - ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_PAD_CFG1 \ + ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x060 */ -#define MXC_R_GPIO_PAD_CFG2 \ - ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_PAD_CFG2 \ + ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x064 */ -#define MXC_R_GPIO_EN1 \ - ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_EN1 \ + ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x068 */ -#define MXC_R_GPIO_EN1_SET \ - ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_EN1_SET \ + ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: <tt> \ 0x0x06C */ -#define MXC_R_GPIO_EN1_CLR \ - ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_EN1_CLR \ + ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x070 */ -#define MXC_R_GPIO_EN2 \ - ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_EN2 \ + ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x074 */ -#define MXC_R_GPIO_EN2_SET \ - ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_EN2_SET \ + ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x078 */ -#define MXC_R_GPIO_EN2_CLR \ - ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_EN2_CLR \ + ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: <tt> \ 0x0x07C */ -#define MXC_R_GPIO_IS \ - ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_IS \ + ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x0A8 */ -#define MXC_R_GPIO_SR \ - ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_SR \ + ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: <tt> \ 0x0x0AC */ -#define MXC_R_GPIO_DS \ - ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_DS \ + ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x0B0 */ -#define MXC_R_GPIO_DS1 \ - ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_DS1 \ + ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x0B4 */ -#define MXC_R_GPIO_PS \ - ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_PS \ + ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x0B8 */ -#define MXC_R_GPIO_VSSEL \ - ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> \ +#define MXC_R_GPIO_VSSEL \ + ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: <tt> \ 0x0x0C0 */ /** @@ -277,19 +277,26 @@ typedef enum { * setting for one GPIO pin on the associated port. */ #define MXC_F_GPIO_EN_GPIO_EN_POS 0 /**< EN_GPIO_EN Position */ -#define MXC_F_GPIO_EN_GPIO_EN \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< EN_GPIO_EN Mask */ -#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ +#define MXC_F_GPIO_EN_GPIO_EN \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_GPIO_EN_POS)) /**< \ + EN_GPIO_EN \ + Mask */ +#define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ ((uint32_t)0x0UL) /**< EN_GPIO_EN_ALTERNATE Value */ -#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE \ - (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ - << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_ALTERNATE Setting */ -#define MXC_V_GPIO_EN_GPIO_EN_GPIO \ +#define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE \ + (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE \ + << MXC_F_GPIO_EN_GPIO_EN_POS) /**< \ + EN_GPIO_EN_ALTERNATE \ + Setting \ + */ +#define MXC_V_GPIO_EN_GPIO_EN_GPIO \ ((uint32_t)0x1UL) /**< EN_GPIO_EN_GPIO Value */ -#define MXC_S_GPIO_EN_GPIO_EN_GPIO \ - (MXC_V_GPIO_EN_GPIO_EN_GPIO \ - << MXC_F_GPIO_EN_GPIO_EN_POS) /**< EN_GPIO_EN_GPIO Setting */ +#define MXC_S_GPIO_EN_GPIO_EN_GPIO \ + (MXC_V_GPIO_EN_GPIO_EN_GPIO \ + << MXC_F_GPIO_EN_GPIO_EN_POS) /**< \ + EN_GPIO_EN_GPIO \ + Setting \ + */ /** * GPIO Set Function Enable Register. Writing a 1 to one or more bits @@ -297,9 +304,10 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN_SET_ALL_POS 0 /**< EN_SET_ALL Position */ -#define MXC_F_GPIO_EN_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN_SET_ALL_POS)) /**< EN_SET_ALL Mask */ +#define MXC_F_GPIO_EN_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_SET_ALL_POS)) /**< \ + EN_SET_ALL \ + Mask */ /** * GPIO Clear Function Enable Register. Writing a 1 to one or more @@ -307,33 +315,34 @@ typedef enum { * without affecting other bits in that register. */ #define MXC_F_GPIO_EN_CLR_ALL_POS 0 /**< EN_CLR_ALL Position */ -#define MXC_F_GPIO_EN_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< EN_CLR_ALL Mask */ +#define MXC_F_GPIO_EN_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN_CLR_ALL_POS)) /**< \ + EN_CLR_ALL \ + Mask */ /** * GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN * setting for one GPIO pin in the associated port. */ -#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS \ - 0 /**< OUT_EN_GPIO_OUT_EN Position \ +#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS \ + 0 /**< OUT_EN_GPIO_OUT_EN Position \ */ -#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< OUT_EN_GPIO_OUT_EN \ - Mask */ -#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ +#define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) /**< \ + OUT_EN_GPIO_OUT_EN \ + Mask */ +#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ ((uint32_t)0x0UL) /**< OUT_EN_GPIO_OUT_EN_DIS Value */ -#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ - (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ - << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS \ +#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ + (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS \ + << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_DIS \ Setting */ -#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \ +#define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \ ((uint32_t)0x1UL) /**< OUT_EN_GPIO_OUT_EN_EN Value */ -#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN \ - (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \ - << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN \ +#define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN \ + (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN \ + << MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) /**< OUT_EN_GPIO_OUT_EN_EN \ Setting */ /** @@ -342,10 +351,11 @@ typedef enum { * GPIO_OUT_EN to 1, without affecting other bits in that register. */ #define MXC_F_GPIO_OUT_EN_SET_ALL_POS 0 /**< OUT_EN_SET_ALL Position */ -#define MXC_F_GPIO_OUT_EN_SET_ALL \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< OUT_EN_SET_ALL Mask */ +#define MXC_F_GPIO_OUT_EN_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_EN_SET_ALL_POS)) /**< \ + OUT_EN_SET_ALL \ + Mask */ /** * GPIO Output Enable Clear Function Enable Register. Writing a 1 to @@ -353,10 +363,11 @@ typedef enum { * GPIO_OUT_EN to 0, without affecting other bits in that register. */ #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS 0 /**< OUT_EN_CLR_ALL Position */ -#define MXC_F_GPIO_OUT_EN_CLR_ALL \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< OUT_EN_CLR_ALL Mask */ +#define MXC_F_GPIO_OUT_EN_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) /**< \ + OUT_EN_CLR_ALL \ + Mask */ /** * GPIO Output Register. Each bit controls the GPIO_OUT setting for @@ -364,40 +375,47 @@ typedef enum { * directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. */ #define MXC_F_GPIO_OUT_GPIO_OUT_POS 0 /**< OUT_GPIO_OUT Position */ -#define MXC_F_GPIO_OUT_GPIO_OUT \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< OUT_GPIO_OUT Mask */ -#define MXC_V_GPIO_OUT_GPIO_OUT_LOW \ +#define MXC_F_GPIO_OUT_GPIO_OUT \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_GPIO_OUT_POS)) /**< \ + OUT_GPIO_OUT \ + Mask */ +#define MXC_V_GPIO_OUT_GPIO_OUT_LOW \ ((uint32_t)0x0UL) /**< OUT_GPIO_OUT_LOW Value */ -#define MXC_S_GPIO_OUT_GPIO_OUT_LOW \ - (MXC_V_GPIO_OUT_GPIO_OUT_LOW \ - << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_LOW Setting */ -#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ +#define MXC_S_GPIO_OUT_GPIO_OUT_LOW \ + (MXC_V_GPIO_OUT_GPIO_OUT_LOW \ + << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< \ + OUT_GPIO_OUT_LOW \ + Setting \ + */ +#define MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ ((uint32_t)0x1UL) /**< OUT_GPIO_OUT_HIGH Value */ -#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH \ - (MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ - << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< OUT_GPIO_OUT_HIGH Setting */ +#define MXC_S_GPIO_OUT_GPIO_OUT_HIGH \ + (MXC_V_GPIO_OUT_GPIO_OUT_HIGH \ + << MXC_F_GPIO_OUT_GPIO_OUT_POS) /**< \ + OUT_GPIO_OUT_HIGH \ + Setting \ + */ /** * GPIO Output Set. Writing a 1 to one or more bits in this register * sets the bits in the same positions in GPIO_OUT to 1, without affecting other * bits in that register. */ -#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS \ +#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS \ 0 /**< OUT_SET_GPIO_OUT_SET Position */ -#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< \ - OUT_SET_GPIO_OUT_SET \ - Mask */ -#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \ +#define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) /**< \ + OUT_SET_GPIO_OUT_SET \ + Mask */ +#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \ ((uint32_t)0x0UL) /**< OUT_SET_GPIO_OUT_SET_NO Value */ -#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO \ - (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \ - << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO \ +#define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO \ + (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO \ + << MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) /**< OUT_SET_GPIO_OUT_SET_NO \ Setting */ -#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET \ +#define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET \ ((uint32_t)0x1UL) /**< OUT_SET_GPIO_OUT_SET_SET Value */ #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET \ (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET \ @@ -408,49 +426,48 @@ typedef enum { * clears the bits in the same positions in GPIO_OUT to 0, without affecting * other bits in that register. */ -#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS \ +#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS \ 0 /**< OUT_CLR_GPIO_OUT_CLR Position */ -#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< \ - OUT_CLR_GPIO_OUT_CLR \ - Mask */ +#define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) /**< \ + OUT_CLR_GPIO_OUT_CLR \ + Mask */ /** * GPIO Input Register. Read-only register to read from the logic * states of the GPIO pins on this port. */ #define MXC_F_GPIO_IN_GPIO_IN_POS 0 /**< IN_GPIO_IN Position */ -#define MXC_F_GPIO_IN_GPIO_IN \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< IN_GPIO_IN Mask */ +#define MXC_F_GPIO_IN_GPIO_IN \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_GPIO_IN_POS)) /**< \ + IN_GPIO_IN \ + Mask */ /** * GPIO Interrupt Mode Register. Each bit in this register controls * the interrupt mode setting for the associated GPIO pin on this port. */ -#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS \ +#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS \ 0 /**< INT_MOD_GPIO_INT_MOD Position */ -#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< \ - INT_MOD_GPIO_INT_MOD \ - Mask */ -#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ +#define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) /**< \ + INT_MOD_GPIO_INT_MOD \ + Mask */ +#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ ((uint32_t)0x0UL) /**< INT_MOD_GPIO_INT_MOD_LEVEL Value */ #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL \ << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< \ INT_MOD_GPIO_INT_MOD_LEVEL \ Setting */ -#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ +#define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ ((uint32_t)0x1UL) /**< INT_MOD_GPIO_INT_MOD_EDGE Value */ -#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ - (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ - << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< \ - INT_MOD_GPIO_INT_MOD_EDGE \ +#define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ + (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE \ + << MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) /**< \ + INT_MOD_GPIO_INT_MOD_EDGE \ Setting */ /** @@ -458,22 +475,21 @@ typedef enum { * controls the interrupt polarity setting for one GPIO pin in the associated * port. */ -#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS \ +#define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS \ 0 /**< INT_POL_GPIO_INT_POL Position */ -#define MXC_F_GPIO_INT_POL_GPIO_INT_POL \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< \ - INT_POL_GPIO_INT_POL \ - Mask */ -#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING \ +#define MXC_F_GPIO_INT_POL_GPIO_INT_POL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) /**< \ + INT_POL_GPIO_INT_POL \ + Mask */ +#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING \ ((uint32_t)0x0UL) /**< INT_POL_GPIO_INT_POL_FALLING Value */ #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING \ (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING \ << MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) /**< \ INT_POL_GPIO_INT_POL_FALLING \ Setting */ -#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING \ +#define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING \ ((uint32_t)0x1UL) /**< INT_POL_GPIO_INT_POL_RISING Value */ #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING \ (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING \ @@ -485,25 +501,25 @@ typedef enum { * GPIO Interrupt Enable Register. Each bit in this register controls * the GPIO interrupt enable for the associated pin on the GPIO port. */ -#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS \ - 0 /**< INT_EN_GPIO_INT_EN Position \ +#define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS \ + 0 /**< INT_EN_GPIO_INT_EN Position \ */ -#define MXC_F_GPIO_INT_EN_GPIO_INT_EN \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< INT_EN_GPIO_INT_EN \ - Mask */ -#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \ +#define MXC_F_GPIO_INT_EN_GPIO_INT_EN \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) /**< \ + INT_EN_GPIO_INT_EN \ + Mask */ +#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \ ((uint32_t)0x0UL) /**< INT_EN_GPIO_INT_EN_DIS Value */ -#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS \ - (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \ - << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS \ +#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS \ + (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS \ + << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_DIS \ Setting */ -#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \ +#define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \ ((uint32_t)0x1UL) /**< INT_EN_GPIO_INT_EN_EN Value */ -#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN \ - (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \ - << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN \ +#define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN \ + (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN \ + << MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) /**< INT_EN_GPIO_INT_EN_EN \ Setting */ /** @@ -511,22 +527,21 @@ typedef enum { * register sets the bits in the same positions in GPIO_INT_EN to 1, without * affecting other bits in that register. */ -#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS \ +#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS \ 0 /**< INT_EN_SET_GPIO_INT_EN_SET Position */ -#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< \ - INT_EN_SET_GPIO_INT_EN_SET \ - Mask */ -#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ +#define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) /**< \ + INT_EN_SET_GPIO_INT_EN_SET \ + Mask */ +#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ ((uint32_t)0x0UL) /**< INT_EN_SET_GPIO_INT_EN_SET_NO Value */ #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO \ << MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) /**< \ INT_EN_SET_GPIO_INT_EN_SET_NO \ Setting */ -#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ +#define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ ((uint32_t)0x1UL) /**< INT_EN_SET_GPIO_INT_EN_SET_SET Value */ #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET \ @@ -538,22 +553,21 @@ typedef enum { * this register clears the bits in the same positions in GPIO_INT_EN to 0, * without affecting other bits in that register. */ -#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS \ +#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS \ 0 /**< INT_EN_CLR_GPIO_INT_EN_CLR Position */ -#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< \ - INT_EN_CLR_GPIO_INT_EN_CLR \ - Mask */ -#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ +#define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) /**< \ + INT_EN_CLR_GPIO_INT_EN_CLR \ + Mask */ +#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ ((uint32_t)0x0UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_NO Value */ #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO \ << MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) /**< \ INT_EN_CLR_GPIO_INT_EN_CLR_NO \ Setting */ -#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ +#define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ ((uint32_t)0x1UL) /**< INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR Value */ #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR \ @@ -564,22 +578,21 @@ typedef enum { * GPIO Interrupt Status Register. Each bit in this register contains * the pending interrupt status for the associated GPIO pin in this port. */ -#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS \ +#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS \ 0 /**< INT_STAT_GPIO_INT_STAT Position */ -#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< \ - INT_STAT_GPIO_INT_STAT \ - Mask */ -#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO \ +#define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) /**< \ + INT_STAT_GPIO_INT_STAT \ + Mask */ +#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO \ ((uint32_t)0x0UL) /**< INT_STAT_GPIO_INT_STAT_NO Value */ #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO \ (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO \ << MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) /**< \ INT_STAT_GPIO_INT_STAT_NO \ Setting */ -#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ +#define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ ((uint32_t)0x1UL) /**< INT_STAT_GPIO_INT_STAT_PENDING Value */ #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING \ @@ -593,33 +606,34 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_INT_CLR_ALL_POS 0 /**< INT_CLR_ALL Position */ -#define MXC_F_GPIO_INT_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< INT_CLR_ALL Mask */ +#define MXC_F_GPIO_INT_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_CLR_ALL_POS)) /**< \ + INT_CLR_ALL \ + Mask */ /** * GPIO Wake Enable Register. Each bit in this register controls the * PMU wakeup enable for the associated GPIO pin in this port. */ -#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS \ +#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS \ 0 /**< WAKE_EN_GPIO_WAKE_EN Position */ -#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< \ - WAKE_EN_GPIO_WAKE_EN \ - Mask */ -#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ +#define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) /**< \ + WAKE_EN_GPIO_WAKE_EN \ + Mask */ +#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ ((uint32_t)0x0UL) /**< WAKE_EN_GPIO_WAKE_EN_DIS Value */ #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS \ << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_DIS \ Setting */ -#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ +#define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ ((uint32_t)0x1UL) /**< WAKE_EN_GPIO_WAKE_EN_EN Value */ -#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ - (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ - << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN \ +#define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ + (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN \ + << MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) /**< WAKE_EN_GPIO_WAKE_EN_EN \ Setting */ /** @@ -628,9 +642,9 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS 0 /**< WAKE_EN_SET_ALL Position */ -#define MXC_F_GPIO_WAKE_EN_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL \ +#define MXC_F_GPIO_WAKE_EN_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) /**< WAKE_EN_SET_ALL \ Mask */ /** @@ -639,32 +653,31 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS 0 /**< WAKE_EN_CLR_ALL Position */ -#define MXC_F_GPIO_WAKE_EN_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL \ +#define MXC_F_GPIO_WAKE_EN_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) /**< WAKE_EN_CLR_ALL \ Mask */ /** * GPIO Interrupt Dual Edge Mode Register. Each bit in this register * selects dual edge mode for the associated GPIO pin in this port. */ -#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS \ +#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS \ 0 /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE Position */ -#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< \ - INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \ - Mask \ - */ -#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ +#define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) /**< \ + INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE \ + Mask \ + */ +#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ ((uint32_t)0x0UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO Value */ #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ << MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) /**< \ INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO \ Setting */ -#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ +#define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ ((uint32_t)0x1UL) /**< INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN Value */ #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN \ @@ -676,29 +689,28 @@ typedef enum { * GPIO Input Mode Config 1. Each bit in this register enables the * weak pull-up for the associated GPIO pin in this port. */ -#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS \ +#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS \ 0 /**< PAD_CFG1_GPIO_PAD_CFG1 Position */ -#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< \ - PAD_CFG1_GPIO_PAD_CFG1 \ - Mask */ -#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ +#define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1 \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) /**< \ + PAD_CFG1_GPIO_PAD_CFG1 \ + Mask */ +#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ ((uint32_t)0x0UL) /**< PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE Value */ #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< \ PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE \ Setting */ -#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ +#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ ((uint32_t)0x1UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PU Value */ #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU \ << MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) /**< \ PAD_CFG1_GPIO_PAD_CFG1_PU \ Setting */ -#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ +#define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ ((uint32_t)0x2UL) /**< PAD_CFG1_GPIO_PAD_CFG1_PD Value */ #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD \ @@ -710,29 +722,28 @@ typedef enum { * GPIO Input Mode Config 2. Each bit in this register enables the * weak pull-up for the associated GPIO pin in this port. */ -#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS \ +#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS \ 0 /**< PAD_CFG2_GPIO_PAD_CFG2 Position */ -#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 \ - ((uint32_t)( \ - 0xFFFFFFFFUL \ - << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< \ - PAD_CFG2_GPIO_PAD_CFG2 \ - Mask */ -#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ +#define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2 \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) /**< \ + PAD_CFG2_GPIO_PAD_CFG2 \ + Mask */ +#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ ((uint32_t)0x0UL) /**< PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE Value */ #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< \ PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE \ Setting */ -#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ +#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ ((uint32_t)0x1UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PU Value */ #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU \ << MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) /**< \ PAD_CFG2_GPIO_PAD_CFG2_PU \ Setting */ -#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ +#define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ ((uint32_t)0x2UL) /**< PAD_CFG2_GPIO_PAD_CFG2_PD Value */ #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD \ @@ -746,19 +757,24 @@ typedef enum { * this port. */ #define MXC_F_GPIO_EN1_GPIO_EN1_POS 0 /**< EN1_GPIO_EN1 Position */ -#define MXC_F_GPIO_EN1_GPIO_EN1 \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< EN1_GPIO_EN1 Mask */ -#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ +#define MXC_F_GPIO_EN1_GPIO_EN1 \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN1_GPIO_EN1_POS)) /**< \ + EN1_GPIO_EN1 \ + Mask */ +#define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ ((uint32_t)0x0UL) /**< EN1_GPIO_EN1_PRIMARY Value */ -#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY \ - (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ - << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_PRIMARY Setting */ -#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ +#define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY \ + (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY \ + << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< \ + EN1_GPIO_EN1_PRIMARY \ + Setting \ + */ +#define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ ((uint32_t)0x1UL) /**< EN1_GPIO_EN1_SECONDARY Value */ -#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY \ - (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ - << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting \ +#define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY \ + (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY \ + << MXC_F_GPIO_EN1_GPIO_EN1_POS) /**< EN1_GPIO_EN1_SECONDARY Setting \ */ /** @@ -767,9 +783,11 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ -#define MXC_F_GPIO_EN1_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ +#define MXC_F_GPIO_EN1_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< \ + EN1_SET_ALL \ + Mask */ /** * GPIO Alternate Function Clear. Writing a 1 to one or more bits in @@ -777,9 +795,11 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ -#define MXC_F_GPIO_EN1_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ +#define MXC_F_GPIO_EN1_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< \ + EN1_CLR_ALL \ + Mask */ /** * GPIO Alternate Function Enable Register. Each bit in this register @@ -787,19 +807,24 @@ typedef enum { * this port. */ #define MXC_F_GPIO_EN2_GPIO_EN2_POS 0 /**< EN2_GPIO_EN2 Position */ -#define MXC_F_GPIO_EN2_GPIO_EN2 \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< EN2_GPIO_EN2 Mask */ -#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ +#define MXC_F_GPIO_EN2_GPIO_EN2 \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN2_GPIO_EN2_POS)) /**< \ + EN2_GPIO_EN2 \ + Mask */ +#define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ ((uint32_t)0x0UL) /**< EN2_GPIO_EN2_PRIMARY Value */ -#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY \ - (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ - << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_PRIMARY Setting */ -#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ +#define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY \ + (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY \ + << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< \ + EN2_GPIO_EN2_PRIMARY \ + Setting \ + */ +#define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ ((uint32_t)0x1UL) /**< EN2_GPIO_EN2_SECONDARY Value */ -#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY \ - (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ - << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting \ +#define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY \ + (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY \ + << MXC_F_GPIO_EN2_GPIO_EN2_POS) /**< EN2_GPIO_EN2_SECONDARY Setting \ */ /** @@ -808,9 +833,11 @@ typedef enum { * affecting other bits in that register. */ #define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ -#define MXC_F_GPIO_EN2_SET_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ +#define MXC_F_GPIO_EN2_SET_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< \ + EN2_SET_ALL \ + Mask */ /** * GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits @@ -818,9 +845,11 @@ typedef enum { * without affecting other bits in that register. */ #define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ -#define MXC_F_GPIO_EN2_CLR_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ +#define MXC_F_GPIO_EN2_CLR_ALL \ + ((uint32_t)(0xFFFFFFFFUL \ + << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< \ + EN2_CLR_ALL \ + Mask */ /** * GPIO Drive Strength Register. Each bit in this register selects @@ -828,13 +857,13 @@ typedef enum { * Datasheet for sink/source current of GPIO pins in each mode. */ #define MXC_F_GPIO_DS_DS_POS 0 /**< DS_DS Position */ -#define MXC_F_GPIO_DS_DS \ +#define MXC_F_GPIO_DS_DS \ ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS_DS_POS)) /**< DS_DS Mask */ #define MXC_V_GPIO_DS_DS_LD ((uint32_t)0x0UL) /**< DS_DS_LD Value */ -#define MXC_S_GPIO_DS_DS_LD \ +#define MXC_S_GPIO_DS_DS_LD \ (MXC_V_GPIO_DS_DS_LD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_LD Setting */ -#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */ -#define MXC_S_GPIO_DS_DS_HD \ +#define MXC_V_GPIO_DS_DS_HD ((uint32_t)0x1UL) /**< DS_DS_HD Value */ +#define MXC_S_GPIO_DS_DS_HD \ (MXC_V_GPIO_DS_DS_HD << MXC_F_GPIO_DS_DS_POS) /**< DS_DS_HD Setting */ /** @@ -844,23 +873,23 @@ typedef enum { */ #define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ #define MXC_F_GPIO_DS1_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask \ + */ /** * GPIO Pull Select Mode. */ #define MXC_F_GPIO_PS_ALL_POS 0 /**< PS_ALL Position */ -#define MXC_F_GPIO_PS_ALL \ - ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask \ +#define MXC_F_GPIO_PS_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PS_ALL_POS)) /**< PS_ALL Mask \ */ /** * GPIO Voltage Select. */ #define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ -#define MXC_F_GPIO_VSSEL_ALL \ - ((uint32_t)(0xFFFFFFFFUL \ - << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ +#define MXC_F_GPIO_VSSEL_ALL \ + ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL \ + Mask */ #endif /* _GPIO_REGS_H_ */ |