diff options
author | Tom Hughes <tomhughes@chromium.org> | 2022-09-21 14:10:01 -0700 |
---|---|---|
committer | Tom Hughes <tomhughes@chromium.org> | 2022-09-22 12:49:33 -0700 |
commit | 2bcf863b492fe7ed8105c853814dba6ed32ba719 (patch) | |
tree | fcf6ce5810f9ff9e3c8cce434812dd75492269ed /chip/max32660/pwrseq_regs.h | |
parent | e5fb0b9ba488614b5684e640530f00821ab7b943 (diff) | |
parent | 28712dae9d7ed1e694f7622cc083afa71090d4d5 (diff) | |
download | chrome-ec-firmware-fpmcu-bloonchipper-release.tar.gz |
Merge remote-tracking branch cros/main into firmware-fpmcu-bloonchipper-releasefirmware-fpmcu-bloonchipper-release
Generated by: ./util/update_release_branch.py --board bloonchipper
--relevant_paths_file ./util/fingerprint-relevant-paths.txt firmware-
fpmcu-bloonchipper-release
Relevant changes:
git log --oneline e5fb0b9ba4..28712dae9d -- board/hatch_fp
board/bloonchipper common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh
ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dc3e9008b8 board/hatch_fp/board.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header
BRANCH=None
BUG=b:246424843 b:234181908 b:244781166 b:234181908 b:244387210
BUG=b:242720240 chromium:1098010 b:180945056 b:236025198 b:234181908
BUG=b:234181908 b:237344361 b:131913998 b:236386294 b:234143158
BUG=b:234781655 b:215613183 b:242720910
TEST=`make -j buildall`
TEST=./test/run_device_tests.py --board bloonchipper
Test "aes": PASSED
Test "cec": PASSED
Test "cortexm_fpu": PASSED
Test "crc": PASSED
Test "flash_physical": PASSED
Test "flash_write_protect": PASSED
Test "fpsensor_hw": PASSED
Test "fpsensor_spi_ro": PASSED
Test "fpsensor_spi_rw": PASSED
Test "fpsensor_uart_ro": PASSED
Test "fpsensor_uart_rw": PASSED
Test "mpu_ro": PASSED
Test "mpu_rw": PASSED
Test "mutex": PASSED
Test "pingpong": PASSED
Test "printf": PASSED
Test "queue": PASSED
Test "rollback_region0": PASSED
Test "rollback_region1": PASSED
Test "rollback_entropy": PASSED
Test "rtc": PASSED
Test "sha256": PASSED
Test "sha256_unrolled": PASSED
Test "static_if": PASSED
Test "stdlib": PASSED
Test "system_is_locked_wp_on": PASSED
Test "system_is_locked_wp_off": PASSED
Test "timer_dos": PASSED
Test "utils": PASSED
Test "utils_str": PASSED
Test "stm32f_rtc": PASSED
Test "panic_data_bloonchipper_v2.0.4277": PASSED
Test "panic_data_bloonchipper_v2.0.5938": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I264ad0ffe7afcd507a1e483c6e934a9c4fea47c3
Diffstat (limited to 'chip/max32660/pwrseq_regs.h')
-rw-r--r-- | chip/max32660/pwrseq_regs.h | 493 |
1 files changed, 253 insertions, 240 deletions
diff --git a/chip/max32660/pwrseq_regs.h b/chip/max32660/pwrseq_regs.h index 1ac0686aa6..e42ab8fd9d 100644 --- a/chip/max32660/pwrseq_regs.h +++ b/chip/max32660/pwrseq_regs.h @@ -1,4 +1,4 @@ -/* Copyright 2019 The Chromium OS Authors. All rights reserved. +/* Copyright 2019 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. */ @@ -53,8 +53,8 @@ extern "C" { */ typedef struct { __IO uint32_t lp_ctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LP_CTRL Register */ - __IO uint32_t - lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL Register */ + __IO uint32_t lp_wakefl; /**< <tt>\b 0x04:</tt> PWRSEQ LP_WAKEFL + Register */ __IO uint32_t lpwk_en; /**< <tt>\b 0x08:</tt> PWRSEQ LPWK_EN Register */ __R uint32_t rsv_0xc_0x3f[13]; __IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */ @@ -64,234 +64,243 @@ typedef struct { * Register offsets for module PWRSEQ * PWRSEQ Peripheral Register Offsets from the PWRSEQ Base */ -#define MXC_R_PWRSEQ_LP_CTRL \ - ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \ \ +#define MXC_R_PWRSEQ_LP_CTRL \ + ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> \ \ \ \ \ 0x0000</tt> */ -#define MXC_R_PWRSEQ_LP_WAKEFL \ - ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \ \ +#define MXC_R_PWRSEQ_LP_WAKEFL \ + ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> \ \ \ \ \ 0x0004</tt> */ -#define MXC_R_PWRSEQ_LPWK_EN \ - ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \ \ +#define MXC_R_PWRSEQ_LPWK_EN \ + ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> \ \ \ \ \ 0x0008</tt> */ -#define MXC_R_PWRSEQ_LPMEMSD \ - ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \ \ +#define MXC_R_PWRSEQ_LPMEMSD \ + ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> \ \ \ \ \ 0x0040</tt> */ /** * pwrseq_registers * Low Power Control Register. */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS \ 0 /**< LP_CTRL_RAMRET_SEL0 Position */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \ \ - LP_CTRL_RAMRET_SEL0 \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0 \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS)) /**< \ \ \ \ \ + LP_CTRL_RAMRET_SEL0 \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL0_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \ (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_DIS \ << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL0_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ - (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN \ +#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ + (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL0_EN \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL0_POS) /**< LP_CTRL_RAMRET_SEL0_EN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS \ 1 /**< LP_CTRL_RAMRET_SEL1 Position */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \ \ - LP_CTRL_RAMRET_SEL1 \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1 \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS)) /**< \ \ \ \ \ + LP_CTRL_RAMRET_SEL1 \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL1_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \ (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_DIS \ << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL1_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ - (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN \ +#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ + (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL1_EN \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL1_POS) /**< LP_CTRL_RAMRET_SEL1_EN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS \ 2 /**< LP_CTRL_RAMRET_SEL2 Position */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \ \ - LP_CTRL_RAMRET_SEL2 \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2 \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS)) /**< \ \ \ \ \ + LP_CTRL_RAMRET_SEL2 \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL2_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \ (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_DIS \ << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL2_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ - (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN \ +#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ + (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL2_EN \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL2_POS) /**< LP_CTRL_RAMRET_SEL2_EN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS \ 3 /**< LP_CTRL_RAMRET_SEL3 Position */ -#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \ \ - LP_CTRL_RAMRET_SEL3 \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3 \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS)) /**< \ \ \ \ \ + LP_CTRL_RAMRET_SEL3 \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_RAMRET_SEL3_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \ (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_DIS \ << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_RAMRET_SEL3_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ - (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ - << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN \ +#define MXC_S_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ + (MXC_V_PWRSEQ_LP_CTRL_RAMRET_SEL3_EN \ + << MXC_F_PWRSEQ_LP_CTRL_RAMRET_SEL3_POS) /**< LP_CTRL_RAMRET_SEL3_EN \ \ \ \ \ Setting */ #define MXC_F_PWRSEQ_LP_CTRL_OVR_POS 4 /**< LP_CTRL_OVR Position */ -#define MXC_F_PWRSEQ_LP_CTRL_OVR \ - ((uint32_t)(0x3UL \ - << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ +#define MXC_F_PWRSEQ_LP_CTRL_OVR \ + ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LP_CTRL_OVR_POS)) /**< LP_CTRL_OVR \ + Mask */ +#define MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ ((uint32_t)0x0UL) /**< LP_CTRL_OVR_0_9V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ - << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_0_9V Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_0_9V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_0_9V \ + << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_0_9V \ + Setting \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ ((uint32_t)0x1UL) /**< LP_CTRL_OVR_1_0V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ - << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_0V Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_0V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_1_0V \ + << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_1_0V \ + Setting \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ ((uint32_t)0x2UL) /**< LP_CTRL_OVR_1_1V Value */ -#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \ - (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ - << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< LP_CTRL_OVR_1_1V Setting */ - -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \ +#define MXC_S_PWRSEQ_LP_CTRL_OVR_1_1V \ + (MXC_V_PWRSEQ_LP_CTRL_OVR_1_1V \ + << MXC_F_PWRSEQ_LP_CTRL_OVR_POS) /**< \ + LP_CTRL_OVR_1_1V \ + Setting \ + */ + +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS \ 6 /**< LP_CTRL_VCORE_DET_BYPASS Position */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ \ \ \ \ - LP_CTRL_VCORE_DET_BYPASS \ - \ \ - \ \ \ \ \ - Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS)) /**< \ + \ \ \ \ \ + LP_CTRL_VCORE_DET_BYPASS \ + \ \ + \ \ \ \ \ + Mask */ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \ ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_DET_BYPASS_ENABLED Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_ENABLED \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_DET_BYPASS_ENABLED \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \ ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_DET_BYPASS_DISABLE Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_DISABLE \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_DET_BYPASS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_DET_BYPASS_DISABLE \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS \ - 8 /**< LP_CTRL_RETREG_EN Position \ \ \ \ \ +#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS \ + 8 /**< LP_CTRL_RETREG_EN Position \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< LP_CTRL_RETREG_EN \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_RETREG_EN \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS)) /**< \ + LP_CTRL_RETREG_EN \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_RETREG_EN_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_DIS \ (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_DIS \ << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_RETREG_EN_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN \ - (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \ - << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \ \ +#define MXC_S_PWRSEQ_LP_CTRL_RETREG_EN_EN \ + (MXC_V_PWRSEQ_LP_CTRL_RETREG_EN_EN \ + << MXC_F_PWRSEQ_LP_CTRL_RETREG_EN_POS) /**< LP_CTRL_RETREG_EN_EN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS \ 10 /**< LP_CTRL_FAST_WK_EN Position */ -#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \ \ - LP_CTRL_FAST_WK_EN \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS)) /**< \ \ \ \ \ + LP_CTRL_FAST_WK_EN \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_FAST_WK_EN_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \ (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_DIS \ << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_FAST_WK_EN_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ - (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ - << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \ \ +#define MXC_S_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ + (MXC_V_PWRSEQ_LP_CTRL_FAST_WK_EN_EN \ + << MXC_F_PWRSEQ_LP_CTRL_FAST_WK_EN_POS) /**< LP_CTRL_FAST_WK_EN_EN \ \ \ \ \ Setting */ #define MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS 11 /**< LP_CTRL_BG_OFF Position */ -#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF \ - ((uint32_t)( \ - 0x1UL << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \ +#define MXC_F_PWRSEQ_LP_CTRL_BG_OFF \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS)) /**< LP_CTRL_BG_OFF \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \ ((uint32_t)0x0UL) /**< LP_CTRL_BG_OFF_ON Value */ -#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON \ - (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \ +#define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_ON \ + (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_ON \ << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_ON Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \ +#define MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \ ((uint32_t)0x1UL) /**< LP_CTRL_BG_OFF_OFF Value */ #define MXC_S_PWRSEQ_LP_CTRL_BG_OFF_OFF \ (MXC_V_PWRSEQ_LP_CTRL_BG_OFF_OFF \ << MXC_F_PWRSEQ_LP_CTRL_BG_OFF_POS) /**< LP_CTRL_BG_OFF_OFF Setting \ \ * \ \ - * \ \ \ - * \ \ \ \ + * \ \ \ + * \ \ \ \ */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS \ 12 /**< LP_CTRL_VCORE_POR_DIS Position */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \ \ - LP_CTRL_VCORE_POR_DIS \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS)) /**< \ \ \ \ \ + LP_CTRL_VCORE_POR_DIS \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \ ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_POR_DIS_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_DIS \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_POR_DIS_DIS \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \ ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_POR_DIS_EN Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_POR_DIS_EN \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_POR_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_POR_DIS_EN \ \ \ \ \ Setting */ @@ -300,70 +309,70 @@ typedef struct { ((uint32_t)(0x1UL \ << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS)) /**< LP_CTRL_LDO_DIS \ \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \ +#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \ ((uint32_t)0x0UL) /**< LP_CTRL_LDO_DIS_EN Value */ -#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN \ - (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \ - << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting \ - * \ \ - * \ \ \ - * \ \ \ \ - * \ \ \ \ \ +#define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_EN \ + (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_EN \ + << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_EN Setting \ + * \ \ + * \ \ \ + * \ \ \ \ + * \ \ \ \ \ */ -#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \ +#define MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \ ((uint32_t)0x1UL) /**< LP_CTRL_LDO_DIS_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_LDO_DIS_DIS \ (MXC_V_PWRSEQ_LP_CTRL_LDO_DIS_DIS \ << MXC_F_PWRSEQ_LP_CTRL_LDO_DIS_POS) /**< LP_CTRL_LDO_DIS_DIS Setting \ * \ \ - * \ \ \ - * \ \ \ \ - * \ \ \ \ \ + * \ \ \ + * \ \ \ \ + * \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS \ 20 /**< LP_CTRL_VCORE_SVM_DIS Position */ -#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \ \ - LP_CTRL_VCORE_SVM_DIS \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \ +#define MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS)) /**< \ \ \ \ \ + LP_CTRL_VCORE_SVM_DIS \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \ ((uint32_t)0x0UL) /**< LP_CTRL_VCORE_SVM_DIS_EN Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_EN \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_SVM_DIS_EN \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \ +#define MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \ ((uint32_t)0x1UL) /**< LP_CTRL_VCORE_SVM_DIS_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \ (MXC_V_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_DIS \ - << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VCORE_SVM_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VCORE_SVM_DIS_DIS \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS \ +#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS \ 25 /**< LP_CTRL_VDDIO_POR_DIS Position */ -#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \ \ - LP_CTRL_VDDIO_POR_DIS \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \ +#define MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS)) /**< \ \ \ \ \ + LP_CTRL_VDDIO_POR_DIS \ + \ \ \ \ Mask \ + */ +#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \ ((uint32_t)0x0UL) /**< LP_CTRL_VDDIO_POR_DIS_EN Value */ #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \ (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_EN \ - << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VDDIO_POR_DIS_EN \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \ +#define MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \ ((uint32_t)0x1UL) /**< LP_CTRL_VDDIO_POR_DIS_DIS Value */ #define MXC_S_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \ (MXC_V_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_DIS \ - << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \ + << MXC_F_PWRSEQ_LP_CTRL_VDDIO_POR_DIS_POS) /**< \ \ \ \ \ LP_CTRL_VDDIO_POR_DIS_DIS \ \ \ \ \ Setting */ @@ -373,10 +382,12 @@ typedef struct { */ #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS 0 /**< LP_WAKEFL_WAKEST Position */ #define MXC_F_PWRSEQ_LP_WAKEFL_WAKEST \ - ((uint32_t)( \ - 0x3FFFUL \ - << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< LP_WAKEFL_WAKEST \ \ - \ \ \ Mask */ + ((uint32_t)(0x3FFFUL \ + << MXC_F_PWRSEQ_LP_WAKEFL_WAKEST_POS)) /**< \ + LP_WAKEFL_WAKEST \ + \ \ + \ \ \ Mask \ + */ /** * pwrseq_registers @@ -384,104 +395,106 @@ typedef struct { * power wakeup functionality for GPIO0. */ #define MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS 0 /**< LPWK_EN_WAKEEN Position */ -#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \ - ((uint32_t)(0x3FFFUL \ - << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< LPWK_EN_WAKEEN \ \ - \ \ \ Mask */ +#define MXC_F_PWRSEQ_LPWK_EN_WAKEEN \ + ((uint32_t)(0x3FFFUL \ + << MXC_F_PWRSEQ_LPWK_EN_WAKEEN_POS)) /**< \ + LPWK_EN_WAKEEN \ + \ \ + \ \ \ Mask \ + */ /** * pwrseq_registers * Low Power Memory Shutdown Control. */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS \ - 0 /**< LPMEMSD_SRAM0_OFF Position \ \ \ \ \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS \ + 0 /**< LPMEMSD_SRAM0_OFF Position \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< LPMEMSD_SRAM0_OFF \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS)) /**< \ + LPMEMSD_SRAM0_OFF \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ ((uint32_t)0x0UL) /**< LPMEMSD_SRAM0_OFF_NORMAL Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_NORMAL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< LPMEMSD_SRAM0_OFF_NORMAL \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ ((uint32_t)0x1UL) /**< LPMEMSD_SRAM0_OFF_SHUTDOWN Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \ \ - LPMEMSD_SRAM0_OFF_SHUTDOWN \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM0_OFF_SHUTDOWN \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM0_OFF_POS) /**< \ \ \ \ \ + LPMEMSD_SRAM0_OFF_SHUTDOWN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS \ - 1 /**< LPMEMSD_SRAM1_OFF Position \ \ \ \ \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS \ + 1 /**< LPMEMSD_SRAM1_OFF Position \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< LPMEMSD_SRAM1_OFF \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS)) /**< \ + LPMEMSD_SRAM1_OFF \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ ((uint32_t)0x0UL) /**< LPMEMSD_SRAM1_OFF_NORMAL Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_NORMAL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< LPMEMSD_SRAM1_OFF_NORMAL \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ ((uint32_t)0x1UL) /**< LPMEMSD_SRAM1_OFF_SHUTDOWN Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \ \ - LPMEMSD_SRAM1_OFF_SHUTDOWN \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM1_OFF_SHUTDOWN \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM1_OFF_POS) /**< \ \ \ \ \ + LPMEMSD_SRAM1_OFF_SHUTDOWN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS \ - 2 /**< LPMEMSD_SRAM2_OFF Position \ \ \ \ \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS \ + 2 /**< LPMEMSD_SRAM2_OFF Position \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< LPMEMSD_SRAM2_OFF \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS)) /**< \ + LPMEMSD_SRAM2_OFF \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ ((uint32_t)0x0UL) /**< LPMEMSD_SRAM2_OFF_NORMAL Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_NORMAL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< LPMEMSD_SRAM2_OFF_NORMAL \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ ((uint32_t)0x1UL) /**< LPMEMSD_SRAM2_OFF_SHUTDOWN Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \ \ - LPMEMSD_SRAM2_OFF_SHUTDOWN \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM2_OFF_SHUTDOWN \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM2_OFF_POS) /**< \ \ \ \ \ + LPMEMSD_SRAM2_OFF_SHUTDOWN \ \ \ \ \ Setting */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS \ - 3 /**< LPMEMSD_SRAM3_OFF Position \ \ \ \ \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS \ + 3 /**< LPMEMSD_SRAM3_OFF Position \ \ \ \ \ */ -#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF \ - ((uint32_t)( \ - 0x1UL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< LPMEMSD_SRAM3_OFF \ - \ \ \ \ Mask */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ +#define MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF \ + ((uint32_t)(0x1UL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS)) /**< \ + LPMEMSD_SRAM3_OFF \ + \ \ \ \ Mask */ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ ((uint32_t)0x0UL) /**< LPMEMSD_SRAM3_OFF_NORMAL Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_NORMAL \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< LPMEMSD_SRAM3_OFF_NORMAL \ \ \ \ \ Setting */ -#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ +#define MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ ((uint32_t)0x1UL) /**< LPMEMSD_SRAM3_OFF_SHUTDOWN Value */ -#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ - (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ - << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \ \ - LPMEMSD_SRAM3_OFF_SHUTDOWN \ +#define MXC_S_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ + (MXC_V_PWRSEQ_LPMEMSD_SRAM3_OFF_SHUTDOWN \ + << MXC_F_PWRSEQ_LPMEMSD_SRAM3_OFF_POS) /**< \ \ \ \ \ + LPMEMSD_SRAM3_OFF_SHUTDOWN \ \ \ \ \ Setting */ - #ifdef __cplusplus } #endif |