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| author | Scott Worley <scott.worley@microchip.corp-partner.google.com> | 2020-12-18 20:09:12 -0500 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-02-10 02:27:28 +0000 |
| commit | f24544e608d3fdf7f79aa8e619e53f76ae7fe96d (patch) | |
| tree | d3d0887af14caf4d488d1951f18cf186c2ca043c /chip/mchp/config_flash_layout.h | |
| parent | e1cc1ca2e1b61a932493f5d55f2da411e5e22d9f (diff) | |
| download | chrome-ec-f24544e608d3fdf7f79aa8e619e53f76ae7fe96d.tar.gz | |
mchp: MEC152x chip configuration and flash layout changes
Update chip configuration and flash layout for MEC152x.
MEC152x Boot-ROM SPI loader uses a different SPI image
header layout.
BRANCH=none
BUG=b:177463787
TEST=Booted skylake RVP to Chrome OS
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Change-Id: Ib88960e545b50d5f4c7906eea85dcee736fee31b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601200
Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
Diffstat (limited to 'chip/mchp/config_flash_layout.h')
| -rw-r--r-- | chip/mchp/config_flash_layout.h | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/chip/mchp/config_flash_layout.h b/chip/mchp/config_flash_layout.h index b25ab02b06..4360df6a53 100644 --- a/chip/mchp/config_flash_layout.h +++ b/chip/mchp/config_flash_layout.h @@ -21,7 +21,7 @@ #define CONFIG_SPI_FLASH /* - * MEC17xx BootROM uses two 4-byte TAG's at SPI offset 0x0 and 0x04. + * MEC170x/MEC152x BootROM uses two 4-byte TAG's at SPI offset 0x0 and 0x04. * One valid TAG must be present. * TAG's point to a Header which must be located on a 256 byte * boundary anywhere in the flash (24-bit addressing). @@ -81,21 +81,29 @@ * of SPI flash and header + binary(LFW+EC_RO) an offset aligned on * a 256 byte boundary. * NOTE: Changing CONFIG_BOOT_HEADER_STORAGE_OFF requires changing - * parameter --payload_offset of pack_ec.py in build.mk! + * parameter --payload_offset parameter in build.mk passed to the + * python image builder. * Two 4-byte TAG's exist at offset 0 and 4 in the SPI flash device. * We only use first TAG pointing to LFW + EC_RO. - * Header size is 128 bytes. Firmware binary is located immediately - * after the header. + * MEC170x Header size is 128 bytes. + * MEC152x Header size is 320 bytes. + * Firmware binary is located immediately after the header. * Second half of SPI flash contains: - * Header(128 bytes) + EC_RW - * EC flash erase/write commands check alginment base on + * Header(128/320 bytes) + EC_RW + * EC flash erase/write commands check alignment base on * CONFIG_FLASH_ERASE_SIZE defined in config_chip.h * NOTE: EC_RO and EC_RW must start at CONFIG_FLASH_ERASE_SIZE or * greater aligned boundaries. */ #define CONFIG_BOOT_HEADER_STORAGE_OFF 0x1000 #define CONFIG_RW_BOOT_HEADER_STORAGE_OFF 0 +#if defined(CHIP_FAMILY_MEC152X) +#define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x140 +#elif defined(CHIP_FAMILY_MEC170X) #define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x80 +#else +#error "FORCED BUILD ERROR: CHIP_FAMILY_xxxx not set or invalid" +#endif #define CONFIG_RW_BOOT_HEADER_STORAGE_SIZE 0 /* Loader / lfw image immediately follows the boot header on SPI */ |