Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release

Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release

Relevant changes:

git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "panic_data_dartmonkey_v2.0.2887": PASSED
     Test "panic_data_nocturne_fp_v2.2.64": PASSED
     Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>

Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7

1 files changed, 76 insertions, 73 deletions

diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c
index 2aaef83dfe..2b21d17dc4 100644
--- a/chip/mchp/i2c.c
+++ b/chip/mchp/i2c.c
@@ -1,4 +1,4 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+/* Copyright 2017 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -24,77 +24,77 @@
 /*
  * MCHP I2C BAUD clock source is 16 MHz.
  */
-#define I2C_CLOCK			16000000UL
-#define MCHP_I2C_SUPPORTED_BUS_CLOCKS	6
+#define I2C_CLOCK 16000000UL
+#define MCHP_I2C_SUPPORTED_BUS_CLOCKS 6
 
 /* SMBus Timing values for 1MHz Speed */
-#define SPEED_1MHZ_BUS_CLOCK		0x0509ul
-#define SPEED_1MHZ_DATA_TIMING		0x06060601ul
-#define SPEED_1MHZ_DATA_TIMING_2	0x06ul
-#define SPEED_1MHZ_IDLE_SCALING		0x01000050ul
-#define SPEED_1MHZ_TIMEOUT_SCALING	0x149CC2C7ul
+#define SPEED_1MHZ_BUS_CLOCK 0x0509ul
+#define SPEED_1MHZ_DATA_TIMING 0x06060601ul
+#define SPEED_1MHZ_DATA_TIMING_2 0x06ul
+#define SPEED_1MHZ_IDLE_SCALING 0x01000050ul
+#define SPEED_1MHZ_TIMEOUT_SCALING 0x149CC2C7ul
 /* SMBus Timing values for 400kHz speed */
-#define SPEED_400KHZ_BUS_CLOCK		0x0F17ul
-#define SPEED_400KHZ_DATA_TIMING	0x040A0F01ul
-#define SPEED_400KHZ_DATA_TIMING_2	0x0Aul
-#define SPEED_400KHZ_IDLE_SCALING	0x01000050ul
-#define SPEED_400KHZ_TIMEOUT_SCALING	0x149CC2C7ul
+#define SPEED_400KHZ_BUS_CLOCK 0x0F17ul
+#define SPEED_400KHZ_DATA_TIMING 0x040A0F01ul
+#define SPEED_400KHZ_DATA_TIMING_2 0x0Aul
+#define SPEED_400KHZ_IDLE_SCALING 0x01000050ul
+#define SPEED_400KHZ_TIMEOUT_SCALING 0x149CC2C7ul
 /* SMBus Timing values for 100kHz speed */
-#define SPEED_100KHZ_BUS_CLOCK		0x4F4Ful
-#define SPEED_100KHZ_DATA_TIMING	0x0C4D4306ul
-#define SPEED_100KHZ_DATA_TIMING_2	0x4Dul
-#define SPEED_100KHZ_IDLE_SCALING	0x01FC01EDul
-#define SPEED_100KHZ_TIMEOUT_SCALING	0x4B9CC2C7ul
+#define SPEED_100KHZ_BUS_CLOCK 0x4F4Ful
+#define SPEED_100KHZ_DATA_TIMING 0x0C4D4306ul
+#define SPEED_100KHZ_DATA_TIMING_2 0x4Dul
+#define SPEED_100KHZ_IDLE_SCALING 0x01FC01EDul
+#define SPEED_100KHZ_TIMEOUT_SCALING 0x4B9CC2C7ul
 /* Bus clock dividers for 333, 80, and 40 kHz */
-#define SPEED_333KHZ_BUS_CLOCK		0x0F1Ful
-#define SPEED_80KHZ_BUS_CLOCK		0x6363ul
-#define SPEED_40KHZ_BUS_CLOCK		0xC7C7ul
+#define SPEED_333KHZ_BUS_CLOCK 0x0F1Ful
+#define SPEED_80KHZ_BUS_CLOCK 0x6363ul
+#define SPEED_40KHZ_BUS_CLOCK 0xC7C7ul
 
 /* Status */
-#define STS_NBB			BIT(0) /* Bus busy */
-#define STS_LAB			BIT(1) /* Arbitration lost */
-#define STS_LRB			BIT(3) /* Last received bit */
-#define STS_BER			BIT(4) /* Bus error */
-#define STS_PIN			BIT(7) /* Pending interrupt */
+#define STS_NBB BIT(0) /* Bus busy */
+#define STS_LAB BIT(1) /* Arbitration lost */
+#define STS_LRB BIT(3) /* Last received bit */
+#define STS_BER BIT(4) /* Bus error */
+#define STS_PIN BIT(7) /* Pending interrupt */
 /* Control */
-#define CTRL_ACK		BIT(0) /* Acknowledge */
-#define CTRL_STO		BIT(1) /* STOP */
-#define CTRL_STA		BIT(2) /* START */
-#define CTRL_ENI		BIT(3) /* Enable interrupt */
-#define CTRL_ESO		BIT(6) /* Enable serial output */
-#define CTRL_PIN		BIT(7) /* Pending interrupt not */
+#define CTRL_ACK BIT(0) /* Acknowledge */
+#define CTRL_STO BIT(1) /* STOP */
+#define CTRL_STA BIT(2) /* START */
+#define CTRL_ENI BIT(3) /* Enable interrupt */
+#define CTRL_ESO BIT(6) /* Enable serial output */
+#define CTRL_PIN BIT(7) /* Pending interrupt not */
 /* Completion */
-#define COMP_DTEN		BIT(2) /* enable device timeouts */
-#define COMP_MCEN		BIT(3) /* enable ctrl. cumulative timeouts */
-#define COMP_SCEN		BIT(4) /* enable periph. cumulative timeouts */
-#define COMP_BIDEN		BIT(5) /* enable Bus idle timeouts */
-#define COMP_IDLE		BIT(29) /* i2c bus is idle */
-#define COMP_RW_BITS_MASK	0x3C /* R/W bits mask */
+#define COMP_DTEN BIT(2) /* enable device timeouts */
+#define COMP_MCEN BIT(3) /* enable ctrl. cumulative timeouts */
+#define COMP_SCEN BIT(4) /* enable periph. cumulative timeouts */
+#define COMP_BIDEN BIT(5) /* enable Bus idle timeouts */
+#define COMP_IDLE BIT(29) /* i2c bus is idle */
+#define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */
 /* Configuration */
-#define CFG_PORT_MASK		(0x0F) /* port selection field */
-#define CFG_TCEN		BIT(4) /* Enable HW bus timeouts */
-#define CFG_FEN			BIT(8) /* enable input filtering */
-#define CFG_RESET		BIT(9) /* reset controller */
-#define CFG_ENABLE		BIT(10) /* enable controller */
-#define CFG_GC_DIS		BIT(14) /* disable general call address */
-#define CFG_ENIDI		BIT(29) /* Enable I2C idle interrupt */
+#define CFG_PORT_MASK (0x0F) /* port selection field */
+#define CFG_TCEN BIT(4) /* Enable HW bus timeouts */
+#define CFG_FEN BIT(8) /* enable input filtering */
+#define CFG_RESET BIT(9) /* reset controller */
+#define CFG_ENABLE BIT(10) /* enable controller */
+#define CFG_GC_DIS BIT(14) /* disable general call address */
+#define CFG_ENIDI BIT(29) /* Enable I2C idle interrupt */
 /* Enable network layer controller done interrupt */
-#define CFG_ENMI		BIT(30)
+#define CFG_ENMI BIT(30)
 /* Enable network layer peripheral done interrupt */
-#define CFG_ENSI		BIT(31)
+#define CFG_ENSI BIT(31)
 /* Controller Command */
-#define MCMD_MRUN		BIT(0)
-#define MCMD_MPROCEED		BIT(1)
-#define MCMD_START0		BIT(8)
-#define MCMD_STARTN		BIT(9)
-#define MCMD_STOP		BIT(10)
-#define MCMD_READM		BIT(12)
-#define MCMD_WCNT_BITPOS	(16)
-#define MCMD_WCNT_MASK0		(0xFF)
-#define MCMD_WCNT_MASK		(0xFF << 16)
-#define MCMD_RCNT_BITPOS	(24)
-#define MCMD_RCNT_MASK0		(0xFF)
-#define MCMD_RCNT_MASK		(0xFF << 24)
+#define MCMD_MRUN BIT(0)
+#define MCMD_MPROCEED BIT(1)
+#define MCMD_START0 BIT(8)
+#define MCMD_STARTN BIT(9)
+#define MCMD_STOP BIT(10)
+#define MCMD_READM BIT(12)
+#define MCMD_WCNT_BITPOS (16)
+#define MCMD_WCNT_MASK0 (0xFF)
+#define MCMD_WCNT_MASK (0xFF << 16)
+#define MCMD_RCNT_BITPOS (24)
+#define MCMD_RCNT_MASK0 (0xFF)
+#define MCMD_RCNT_MASK (0xFF << 24)
 
 /* Maximum transfer of a SMBUS block transfer */
 #define SMBUS_MAX_BLOCK_SIZE 32
@@ -146,34 +146,37 @@ static struct {
 	uint8_t lines;
 } cdata[I2C_CONTROLLER_COUNT];
 
-static const uint16_t i2c_ctrl_nvic_id[] = {
-	MCHP_IRQ_I2C_0, MCHP_IRQ_I2C_1, MCHP_IRQ_I2C_2, MCHP_IRQ_I2C_3,
+static const uint16_t i2c_ctrl_nvic_id[] = { MCHP_IRQ_I2C_0, MCHP_IRQ_I2C_1,
+					     MCHP_IRQ_I2C_2, MCHP_IRQ_I2C_3,
 #if defined(CHIP_FAMILY_MEC172X)
-	MCHP_IRQ_I2C_4
+					     MCHP_IRQ_I2C_4
 #elif defined(CHIP_FAMILY_MEC152X)
-	MCHP_IRQ_I2C_4, MCHP_IRQ_I2C_5, MCHP_IRQ_I2C_6, MCHP_IRQ_I2C_7
+					     MCHP_IRQ_I2C_4, MCHP_IRQ_I2C_5,
+					     MCHP_IRQ_I2C_6, MCHP_IRQ_I2C_7
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_nvic_id) == MCHP_I2C_CTRL_MAX);
 
-static const uint16_t i2c_controller_pcr[] = {
-	MCHP_PCR_I2C0, MCHP_PCR_I2C1, MCHP_PCR_I2C2, MCHP_PCR_I2C3,
+static const uint16_t i2c_controller_pcr[] = { MCHP_PCR_I2C0, MCHP_PCR_I2C1,
+					       MCHP_PCR_I2C2, MCHP_PCR_I2C3,
 #if defined(CHIP_FAMILY_MEC172X)
-	MCHP_PCR_I2C4
+					       MCHP_PCR_I2C4
 #elif defined(CHIP_FAMILY_MEC152X)
 	MCHP_PCR_I2C4, MCHP_PCR_I2C5, MCHP_PCR_I2C6, MCHP_PCR_I2C7,
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(i2c_controller_pcr) == MCHP_I2C_CTRL_MAX);
 
-static uintptr_t i2c_ctrl_base_addr[] = {
-	MCHP_I2C0_BASE, MCHP_I2C1_BASE, MCHP_I2C2_BASE, MCHP_I2C3_BASE,
+static uintptr_t i2c_ctrl_base_addr[] = { MCHP_I2C0_BASE, MCHP_I2C1_BASE,
+					  MCHP_I2C2_BASE, MCHP_I2C3_BASE,
 #if defined(CHIP_FAMILY_MEC172X)
-	MCHP_I2C4_BASE
+					  MCHP_I2C4_BASE
 #elif defined(CHIP_FAMILY_MEC152X)
-	MCHP_I2C4_BASE,
-	/* NOTE: 5-7 do not implement network layer hardware */
-	MCHP_I2C5_BASE, MCHP_I2C6_BASE, MCHP_I2C7_BASE
+					  MCHP_I2C4_BASE,
+					  /* NOTE: 5-7 do not implement network
+					     layer hardware */
+					  MCHP_I2C5_BASE, MCHP_I2C6_BASE,
+					  MCHP_I2C7_BASE
 #endif
 };
 BUILD_ASSERT(ARRAY_SIZE(i2c_ctrl_base_addr) == MCHP_I2C_CTRL_MAX);
@@ -230,7 +233,7 @@ struct i2c_bus_clk {
 };
 
 const struct i2c_bus_clk i2c_freq_tbl[] = {
-	{ 40, SPEED_40KHZ_BUS_CLOCK }, { 80, SPEED_80KHZ_BUS_CLOCK },
+	{ 40, SPEED_40KHZ_BUS_CLOCK },	 { 80, SPEED_80KHZ_BUS_CLOCK },
 	{ 100, SPEED_100KHZ_BUS_CLOCK }, { 333, SPEED_333KHZ_BUS_CLOCK },
 	{ 400, SPEED_400KHZ_BUS_CLOCK }, { 1000, SPEED_1MHZ_BUS_CLOCK },
 };