mchp: MEC152x eSPI adjust number of ACPI EC instances

MEC152X has one fewer ACPI EC instance than MEC170X.
Adjust ACPI EC initialization tables. Update KBC enable
for eSPI mode. Remove MCHP debug trace statements.

BRANCH=none
BUG=b:177463787
TEST=Booted skylake RVP to Chrome OS

Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Change-Id: I97bed09f4eb949e47bc792a76f3bb4d626b8c5b2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601205
Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Ravin Kumar <ravin.kumar@microchip.com>

1 files changed, 26 insertions, 12 deletions

diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c
index 91adb7f17c..8fe37c2247 100644
--- a/chip/mchp/lpc.c
+++ b/chip/mchp/lpc.c
@@ -240,7 +240,7 @@ static void lpc_send_response(struct host_cmd_handler_args *args)
 
 	/*
 	 * Clear processing flag in hardware and
-         * sticky status in interrupt aggregator.
+	 * sticky status in interrupt aggregator.
 	 */
 	MCHP_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING;
 	MCHP_INT_SOURCE(MCHP_ACPI_EC_GIRQ) =
@@ -282,36 +282,47 @@ void lpc_mem_mapped_init(void)
 		EC_HOST_CMD_FLAG_VERSION_3;
 }
 
-const int acpi_ec_pcr_slp[MCHP_ACPI_EC_MAX] = {
+const int acpi_ec_pcr_slp[] = {
 	MCHP_PCR_ACPI_EC0,
 	MCHP_PCR_ACPI_EC1,
 	MCHP_PCR_ACPI_EC2,
 	MCHP_PCR_ACPI_EC3,
+#ifdef CHIP_FAMILY_MEC170X
 	MCHP_PCR_ACPI_EC4,
+#endif
 };
+BUILD_ASSERT(ARRAY_SIZE(acpi_ec_pcr_slp) == MCHP_ACPI_EC_INSTANCES);
 
-const int acpi_ec_nvic_ibf[MCHP_ACPI_EC_MAX] = {
+const int acpi_ec_nvic_ibf[] = {
 	MCHP_IRQ_ACPIEC0_IBF,
 	MCHP_IRQ_ACPIEC1_IBF,
 	MCHP_IRQ_ACPIEC2_IBF,
 	MCHP_IRQ_ACPIEC3_IBF,
+#ifdef CHIP_FAMILY_MEC170X
 	MCHP_IRQ_ACPIEC4_IBF,
+#endif
 };
+BUILD_ASSERT(ARRAY_SIZE(acpi_ec_nvic_ibf) == MCHP_ACPI_EC_INSTANCES);
 
 #ifdef CONFIG_HOSTCMD_ESPI
-const int acpi_ec_espi_bar_id[MCHP_ACPI_EC_MAX] = {
+const int acpi_ec_espi_bar_id[] = {
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC0,
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC1,
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC2,
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC3,
+#ifdef CHIP_FAMILY_MEC170X
 	MCHP_ESPI_IO_BAR_ID_ACPI_EC4,
+#endif
 };
+BUILD_ASSERT(ARRAY_SIZE(acpi_ec_espi_bar_id) == MCHP_ACPI_EC_INSTANCES);
 #endif
 
 void chip_acpi_ec_config(int instance, uint32_t io_base, uint8_t mask)
 {
-	if (instance >= MCHP_ACPI_EC_MAX)
+	if (instance >= MCHP_ACPI_EC_INSTANCES) {
 		CPUTS("ACPI EC CFG invalid");
+		return;
+	}
 
 	MCHP_PCR_SLP_DIS_DEV(acpi_ec_pcr_slp[instance]);
 
@@ -361,8 +372,13 @@ void chip_8042_config(uint32_t io_base)
 #ifndef CONFIG_KEYBOARD_IRQ_GPIO
 	/* Set up SERIRQ for keyboard */
 	MCHP_8042_KB_CTRL |= BIT(5);
+#ifdef CONFIG_HOSTCMD_ESPI
+	/* Delivery 8042 keyboard interrupt as IRQ1 using eSPI SERIRQ */
+	MCHP_ESPI_IO_SERIRQ_REG(MCHP_ESPI_SIRQ_8042_KB) = 1;
+#else
 	MCHP_LPC_SIRQ(1) = 0x01;
 #endif
+#endif
 }
 
 /*
@@ -371,7 +387,7 @@ void chip_8042_config(uint32_t io_base)
  * in SRAM. EMI hardware adds 16-bit offset Host programs into
  * EC_Address_LSB/MSB registers.
  * Limit EMI read / write range. First 256 bytes are RW for host
- * commands. Second 256 bytes are RO for mem-mapped data.
+ * commands. Second 256 bytes are RO for memory-mapped data.
  * Hardware decodes a fixed 16 byte IO range.
  */
 void chip_emi0_config(uint32_t io_base)
@@ -393,9 +409,9 @@ void chip_emi0_config(uint32_t io_base)
 	task_enable_irq(MCHP_IRQ_EMI0);
 }
 
-/* Setup Port80 Debug Hardware ports.
+/* Setup Port 80 Debug Hardware ports.
  * First instance for I/O 80h only.
- * Clear FIFO's and timestamp.
+ * Clear FIFO's and time stamp.
  * Set FIFO interrupt threshold to maximum of 14 bytes.
  */
 void chip_port80_config(uint32_t io_base)
@@ -418,8 +434,8 @@ void chip_port80_config(uint32_t io_base)
 
 	MCHP_P80_ACTIVATE(0) = 1;
 
-	MCHP_INT_SOURCE(15) = MCHP_INT15_P80(0);
-	MCHP_INT_ENABLE(15) = MCHP_INT15_P80(0);
+	MCHP_INT_SOURCE(15) = MCHP_P80_GIRQ_BIT(0);
+	MCHP_INT_ENABLE(15) = MCHP_P80_GIRQ_BIT(0);
 	task_enable_irq(MCHP_IRQ_PORT80DBG0);
 }
 
@@ -449,8 +465,6 @@ static void chip_lpc_iobar_debug(void)
 #ifndef CONFIG_HOSTCMD_ESPI
 static void setup_lpc(void)
 {
-	TRACE0(55, LPC, 0, "setup_lpc");
-
 	MCHP_LPC_CFG_BAR |= (1ul << 15);
 
 	/* Set up ACPI0 for 0x62/0x66 */