mchp: MEC172x update Port 80h and ACPI EC

Update the number of ACPI EC instances: MEC172x and MEC170x
implement 5 whereas MEC152x implements 4. Update Port 80h capture
code for MEC172x BIOS Debug Port (BDP) implementation. BDP implements
a 32 entry FIFO storing 16 bit entries. Each entry contains the
data byte and flags indicating byte lane and FIFO status. BDP does
not include the time stamp counter of MEC170x/MEC152x Port 80h capture
hardware.

BRANCH=none
BUG=none
TEST=Build MCHP MEC170x and MEC15x boards

Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Change-Id: I145619bc16dc1ed292e0c2b3d3d3fe9c6d8ed81d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2749515
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Martin Yan <martin.yan@microchip.corp-partner.google.com>

1 files changed, 36 insertions, 5 deletions

diff --git a/chip/mchp/port80.c b/chip/mchp/port80.c
index 8be91e9d3d..ecfd0b5ebb 100644
--- a/chip/mchp/port80.c
+++ b/chip/mchp/port80.c
@@ -15,15 +15,43 @@
 #include "tfdp_chip.h"
 
 
+#if defined(CHIP_FAMILY_MEC172X)
+/*
+ * MEC172x family implements a new Port 0x80 capture block.
+ * The BDP HW can capture 8, 16, and 32 bit writes.
+ * Interrupt fires when BDP FIFO threshold is reached.
+ * Data can be read from a 16-bit register containing:
+ * b[7:0] data byte
+ * b[9:8] = byte lane
+ * b[11:10]= flags indicating current byte is a single byte or part of
+ * a multi-byte sequence.
+ * b[14:12] = copy of bits[2:0] of the status register
+ * b[15] = 0 reserved
+ * NOTE: The overrun bit could be used to set a flag indicating EC could
+ * not keep up with the host.
+ */
+void port_80_interrupt(void)
+{
+	int d = MCHP_BDP0_DATTR;
+
+	while (d & MCHP_BDP_DATTR_NE) {
+		port_80_write(d & 0xffU);
+		d = MCHP_BDP0_DATTR;
+	}
+
+	MCHP_INT_SOURCE(MCHP_BDP0_GIRQ) = MCHP_BDP0_GIRQ_BIT;
+}
+DECLARE_IRQ(MCHP_IRQ_BDP0, port_80_interrupt, 3);
+#else
 /*
  * Interrupt fires when number of bytes written
  * to eSPI/LPC I/O 80h-81h exceeds Por80_0 FIFO level
  * Issues:
  * 1. eSPI will not break 16-bit I/O into two 8-bit writes
- *    as LPC does. This means Port80 hardware will capture
+ *    as LPC does. This means Port 80h hardware will capture
  *    only bits[7:0] of data.
  * 2. If Host performs write of 16-bit code as consecutive
- *    byte writes the Port80 hardware will capture both but
+ *    byte writes the Port 80h hardware will capture both but
  *    we do not know the order it was written.
  * 3. If Host sometimes writes one byte code to I/O 80h and
  *    sometimes two byte code to I/O 80h/81h how do we determine
@@ -38,8 +66,11 @@ void port_80_interrupt(void)
 	int d;
 
 	while (MCHP_P80_STS(0) & MCHP_P80_STS_NOT_EMPTY) {
-		/* this masks off time stamp d = port_80_read(); */
-		d = MCHP_P80_CAP(0);	/* b[7:0] = data, b[31:8] = timestamp */
+		/*
+		 * This masks off time stamp d = port_80_read();
+		 * b[7:0] = data, b[32:8] = time stamp
+		 */
+		d = MCHP_P80_CAP(0);
 		trace1(0, P80, 0, "Port80h = 0x%02x", (d & 0xff));
 		port_80_write(d & 0xff);
 	}
@@ -47,5 +78,5 @@ void port_80_interrupt(void)
 	MCHP_INT_SOURCE(MCHP_P80_GIRQ) = MCHP_P80_GIRQ_BIT(0);
 }
 DECLARE_IRQ(MCHP_IRQ_PORT80DBG0, port_80_interrupt, 3);
-
+#endif