diff options
| author | Scott Worley <scott.worley@microchip.corp-partner.google.com> | 2021-02-24 21:56:26 -0500 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-03 20:59:51 +0000 |
| commit | f6b68490f1014321f3c482e91f1773e3f78a9d89 (patch) | |
| tree | aedbd76b068ccb337120737ee78455722a3d7c15 /chip/mchp/registers-mec152x.h | |
| parent | ec2a21e143e1f31b9a607b88a725fca62aa01bd4 (diff) | |
| download | chrome-ec-f6b68490f1014321f3c482e91f1773e3f78a9d89.tar.gz | |
mchp: Disable BGPO on pin used in GPIO list
Microchip MEC parts have a small number of GPIO pins that default
to a mode controlled by VBAT powered logic. When configured for VBAT
operation the GPIO control register is bypassed. This change switches
any of these pins in the GPIO list back to GPIO control.
BRANCH=none
BUG=none
TEST=Manually check pins are no longer controlled by VBAT logic.
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Change-Id: I2d78365b61616ccce568810aecd81fe882e90200
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717742
Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Poornima Tom <poornima.tom@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Poornima Tom <poornima.tom@intel.com>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Diffstat (limited to 'chip/mchp/registers-mec152x.h')
| -rw-r--r-- | chip/mchp/registers-mec152x.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/chip/mchp/registers-mec152x.h b/chip/mchp/registers-mec152x.h index cbea8a2d4e..0448632805 100644 --- a/chip/mchp/registers-mec152x.h +++ b/chip/mchp/registers-mec152x.h @@ -181,6 +181,7 @@ #define MCHP_KEYSCAN_BASE 0x40009c00 #define MCHP_VBAT_BASE 0x4000a400 #define MCHP_VBAT_RAM_BASE 0x4000a800 +#define MCHP_WKTIMER_BASE 0x4000ac80 #define MCHP_BBLED_0_BASE 0x4000B800 #define MCHP_INT_BASE 0x4000e000 #define MCHP_EC_BASE 0x4000fc00 |