diff options
| author | Scott Worley <scott.worley@microchip.corp-partner.google.com> | 2020-12-18 20:41:44 -0500 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-02-10 02:27:34 +0000 |
| commit | afa970e21552678c83beb55238f5e8be697a0520 (patch) | |
| tree | aaac3148e64dc8175021997c4d2841b0a3211391 /chip/mchp/registers-mec1701.h | |
| parent | 4a117b86b6e4ea844941689d98127a664d4c864a (diff) | |
| download | chrome-ec-afa970e21552678c83beb55238f5e8be697a0520.tar.gz | |
mchp: MEC152x chip level GPIO updates
Add support for the unimplemented pin macro.
MEC152x GPIO control includes an input pad disable
feature enabled by default to reduce leakage. We add
logic to enable the input pad when the pin is configured.
Note when pad input is disabled the pin can be used as
output, reading the input value always returns 0, and
interrupt detection is disabled. MEC170x does not implement
input pad disable bit. Added a bit define with value 0 to
MEC170x register file so that no condition compile logic
is required.
BRANCH=none
BUG=b:177463787
TEST=Booted skylake RVP to Chrome OS
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Change-Id: Ie5ce58a698311328012440d76eedb1f2ce768d0e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601202
Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
Diffstat (limited to 'chip/mchp/registers-mec1701.h')
| -rw-r--r-- | chip/mchp/registers-mec1701.h | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/chip/mchp/registers-mec1701.h b/chip/mchp/registers-mec1701.h index 90b2d5ef83..4d8ef775df 100644 --- a/chip/mchp/registers-mec1701.h +++ b/chip/mchp/registers-mec1701.h @@ -474,13 +474,12 @@ /* Bit defines for MCHP_PCR_PWR_RST_STS */ #define MCHP_PWR_RST_STS_MASK_RO 0xc8c -#define MCHP_PWR_RST_STS_MASK_RWC 0x170 +#define MCHP_PWR_RST_STS_MASK_RWC 0x060 #define MCHP_PWR_RST_STS_MASK \ ((MCHP_PWR_RST_STS_MASK_RO) | (MCHP_PWR_RST_STS_MASK_RWC)) #define MCHP_PWR_RST_STS_ESPI_CLK_ACT BIT(11) /* RO */ #define MCHP_PWR_RST_STS_32K_ACT BIT(10) /* RO */ -#define MCHP_PWR_RST_STS_WDT BIT(8) /* R/WC */ #define MCHP_PWR_RST_STS_JTAG_RSTN BIT(7) /* RO */ #define MCHP_PWR_RST_STS_SYS BIT(6) /* R/WC */ /* same function, old bit name */ @@ -764,7 +763,7 @@ /* MCHP implements 6 GPIO ports */ #define MCHP_GPIO_MAX_PORT 6 - +#define UNIMPLEMENTED_GPIO_BANK MCHP_GPIO_MAX_PORT /* * In MECxxxx documentation GPIO numbers are octal, each control * register is located on a 32-bit boundary. @@ -811,6 +810,9 @@ #define MCHP_GPIO_CTRL_FUNC_2 (2 << 12) #define MCHP_GPIO_CTRL_FUNC_3 (3 << 12) #define MCHP_GPIO_CTRL_OUT_LVL BIT(16) +/* MEC170x reserved read-only 0 bit. Value set to 0 */ +#define MCHP_GPIO_CTRL_DIS_INPUT_BITPOS 15 +#define MCHP_GPIO_CTRL_DIS_INPUT_BIT 0 /* * GPIO Parallel Input and Output registers. |