diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-04-27 11:22:01 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-05-11 17:30:06 +0000 |
| commit | 200542008dca0aba2490e9993333be430b5fda6f (patch) | |
| tree | 0ae271ba489504f1e55582fcb36c92c8b226c286 /chip/mchp | |
| parent | 6f8dab1033786ac7071e48bc68add2b5ac271c82 (diff) | |
| download | chrome-ec-200542008dca0aba2490e9993333be430b5fda6f.tar.gz | |
treewide: Convert ESPI_DEFAULT_SCI_WIDTH_US to default VWIRE pulse width
In the corresponding bug, Intel has clarified that this SCI# pulse
length requirement is actually for all virtual wires, therefore this
patch renames CONFIG_ESPI_DEFAULT_SCI_WIDTH_US to
CONFIG_ESPI_DEFAULT_VW_WIDTH_US to reflect its broader purpose. All
pulses of virtual wire signals were converted to use this new pulse
width config option, and all GPIO pulses were converted back to their
original value (65 us).
BUG=b:227367177
BRANCH=brya
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1225b3e436cd1dca71c93500538a201d008781b3
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3610694
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'chip/mchp')
| -rw-r--r-- | chip/mchp/espi.c | 3 | ||||
| -rw-r--r-- | chip/mchp/lpc.c | 4 |
2 files changed, 5 insertions, 2 deletions
diff --git a/chip/mchp/espi.c b/chip/mchp/espi.c index 778990b852..763b82ece2 100644 --- a/chip/mchp/espi.c +++ b/chip/mchp/espi.c @@ -708,6 +708,9 @@ int espi_vw_pulse_wire(enum espi_vw_signal signal, int pulse_level) if (rc != EC_SUCCESS) return rc; + /* Ensure a minimum pulse width is met. */ + udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US); + /* drive to requested active state */ rc = espi_vw_s2m_set_w4m(ridx, src_num, level); if (rc != EC_SUCCESS) diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c index b89ef1b065..86cc67fb51 100644 --- a/chip/mchp/lpc.c +++ b/chip/mchp/lpc.c @@ -103,14 +103,14 @@ static void lpc_generate_sci(void) CPUTS("LPC Pulse SCI"); #ifdef CONFIG_SCI_GPIO gpio_set_level(CONFIG_SCI_GPIO, 0); - udelay(CONFIG_ESPI_DEFAULT_SCI_WIDTH_US); + udelay(65); gpio_set_level(CONFIG_SCI_GPIO, 1); #else #ifdef CONFIG_HOST_INTERFACE_ESPI espi_vw_pulse_wire(VW_SCI_L, 0); #else MCHP_ACPI_PM_STS |= 1; - udelay(CONFIG_ESPI_DEFAULT_SCI_WIDTH_US); + udelay(CONFIG_ESPI_DEFAULT_VW_WIDTH_US); MCHP_ACPI_PM_STS &= ~1; #endif #endif |