diff options
author | Sam Hurst <shurst@google.com> | 2020-08-03 13:06:42 -0700 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-08-05 18:41:25 +0000 |
commit | dede4e01ae4c877bb05d671087a6e85a29a0f902 (patch) | |
tree | 8aaaba7b7ce04c059ecd4df4de8a5609492065db /chip/mchp | |
parent | e891cd5ebbb08c9101f1802c2dfcec755718d23f (diff) | |
download | chrome-ec-dede4e01ae4c877bb05d671087a6e85a29a0f902.tar.gz |
ec: change usage of dummy
Google is working to change its source code to use more inclusive
language. To that end, replace the term "dummy" with inclusive
alternatives.
BUG=b:162781382
BRANCH=None
TEST=make -j buildall
`grep -ir dummy *`
The only results are in "private/nordic_keyboard/sdk8.0.0"
which is not our code.
Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Diffstat (limited to 'chip/mchp')
-rw-r--r-- | chip/mchp/clock.c | 6 | ||||
-rw-r--r-- | chip/mchp/config_chip.h | 2 | ||||
-rw-r--r-- | chip/mchp/dma.c | 4 | ||||
-rw-r--r-- | chip/mchp/gpspi.c | 10 | ||||
-rw-r--r-- | chip/mchp/i2c.c | 6 | ||||
-rw-r--r-- | chip/mchp/qmspi.c | 18 | ||||
-rw-r--r-- | chip/mchp/registers.h | 2 | ||||
-rwxr-xr-x | chip/mchp/util/pack_ec.py | 4 |
8 files changed, 26 insertions, 26 deletions
diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c index ad8c47d38e..9fdb058898 100644 --- a/chip/mchp/clock.c +++ b/chip/mchp/clock.c @@ -94,7 +94,7 @@ int clock_get_freq(void) */ void clock_init(void) { - int __attribute__((unused)) dummy; + int __attribute__((unused)) unused; trace0(0, MEC, 0, "Clock Init"); @@ -117,8 +117,8 @@ void clock_init(void) #endif trace0(0, MEC, 0, "PLL OSC is Locked"); #ifndef LFW - dummy = shared_mem_size(); - trace11(0, MEC, 0, "Shared Memory size = 0x%08x", (uint32_t)dummy); + unused = shared_mem_size(); + trace11(0, MEC, 0, "Shared Memory size = 0x%08x", (uint32_t)unused); #endif } diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h index 7a0008958c..747a10a8b8 100644 --- a/chip/mchp/config_chip.h +++ b/chip/mchp/config_chip.h @@ -44,7 +44,7 @@ * MCHP I2C controller is master-slave capable and requires * a slave address be programmed even if used as master only. * Each I2C controller can respond to two slave address. - * Define dummy slave addresses that aren't used on the I2C port(s) + * Define fake slave addresses that aren't used on the I2C port(s) * connected to each controller. */ #define CONFIG_MCHP_I2C0_SLAVE_ADDRS 0xE3E1 diff --git a/chip/mchp/dma.c b/chip/mchp/dma.c index 6c9ed8dd47..982dfa8122 100644 --- a/chip/mchp/dma.c +++ b/chip/mchp/dma.c @@ -43,7 +43,7 @@ void dma_disable(enum dma_channel channel) void dma_disable_all(void) { uint16_t ch; - uint32_t dummy = 0; + uint32_t unused = 0; for (ch = 0; ch < MCHP_DMAC_COUNT; ch++) { /* Abort any current transfer. */ @@ -55,7 +55,7 @@ void dma_disable_all(void) /* Soft-reset the block. */ MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_SRST; - dummy += MCHP_DMA_MAIN_CTRL; + unused += MCHP_DMA_MAIN_CTRL; MCHP_DMA_MAIN_CTRL = MCHP_DMA_MAIN_CTRL_ACT; } diff --git a/chip/mchp/gpspi.c b/chip/mchp/gpspi.c index f8b556d389..4edf57ee11 100644 --- a/chip/mchp/gpspi.c +++ b/chip/mchp/gpspi.c @@ -56,14 +56,14 @@ static int gpspi_wait_byte(const int ctrl) /* NOTE: auto-read must be disabled before calling this routine! */ static void gpspi_rx_fifo_clean(const int ctrl) { - uint8_t dummy = 0; + uint8_t unused = 0; /* If ACTIVE and/or RXFF then clean it */ if ((MCHP_SPI_SR(ctrl) & 0x4) == 0x4) - dummy += MCHP_SPI_RD(ctrl); + unused += MCHP_SPI_RD(ctrl); if ((MCHP_SPI_SR(ctrl) & 0x2) == 0x2) - dummy += MCHP_SPI_RD(ctrl); + unused += MCHP_SPI_RD(ctrl); } /* * NOTE: auto-read must be disabled before calling this routine! @@ -73,7 +73,7 @@ static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen) { int i; int ret; - uint8_t dummy = 0; + uint8_t unused = 0; gpspi_rx_fifo_clean(ctrl); @@ -83,7 +83,7 @@ static int gpspi_tx(const int ctrl, const uint8_t *txdata, int txlen) ret = gpspi_wait_byte(ctrl); if (ret != EC_SUCCESS) break; - dummy += MCHP_SPI_RD(ctrl); + unused += MCHP_SPI_RD(ctrl); } return ret; diff --git a/chip/mchp/i2c.c b/chip/mchp/i2c.c index ab2c75c754..da7136a6b2 100644 --- a/chip/mchp/i2c.c +++ b/chip/mchp/i2c.c @@ -454,7 +454,7 @@ static int wait_byte_done(int controller, uint8_t mask, uint8_t expected) * Switch port by reset and reconfigure to handle cases where * the slave on current port is driving line(s) low. * NOTE: I2C hardware reset only requires one AHB clock, back to back - * writes is OK but we added a dummy write as insurance. + * writes is OK but we added an extra write as insurance. */ static void select_port(int port, int controller) { @@ -465,7 +465,7 @@ static void select_port(int port, int controller) return; MCHP_I2C_CONFIG(controller) |= BIT(9); - MCHP_EC_ID_RO = 0; /* dummy write to read-only as delay */ + MCHP_EC_ID_RO = 0; /* extra write to read-only as delay */ MCHP_I2C_CONFIG(controller) &= ~BIT(9); configure_controller(controller, port_sel, i2c_ports[port].kbps); } @@ -651,7 +651,7 @@ static int i2c_mrx_start(int ctrl) return rv; } /* if STOP requested and last 1 or 2 bytes prepare controller - * to NACK last byte. Do this before read of dummy data so + * to NACK last byte. Do this before read of extra data so * controller is setup to NACK last byte. */ cdata[ctrl].flags |= (1ul << 8); diff --git a/chip/mchp/qmspi.c b/chip/mchp/qmspi.c index 1a5f9576b8..72eaa91d37 100644 --- a/chip/mchp/qmspi.c +++ b/chip/mchp/qmspi.c @@ -436,7 +436,7 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device, * aligned >= 4 bytes and the number of bytes is a multiple of 4. * NOTE on SPI flash commands: * This routine does NOT handle SPI flash commands requiring - * dummy clocks or special mode bytes. Dummy clocks and special mode + * extra clocks or special mode bytes. Extra clocks and special mode * bytes require additional descriptors. For example the flash read * dual command (0x3B): * 1. First descriptor transmits 4 bytes (opcode + 24-bit address) on @@ -444,7 +444,7 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device, * 2. Second descriptor set for 2 IO pins, 2 bytes, TX disabled. When * this descriptor is executed QMSPI will tri-state IO0 & IO1 and * output 8 clocks (dual mode 4 clocks per byte). The SPI flash may - * turn on its output drivers on the first dummy clock. + * turn on its output drivers on the first clock. * 3. Third descriptor set for 2 IO pins, read data using DMA. Unit * size and DMA unit size based on number of bytes to read and * alignment of destination buffer. @@ -455,14 +455,14 @@ uint8_t qmspi_xfr(const struct spi_device_t *spi_device, * the SPI flash that changes the default 24-bit address command to * require a 32-bit address. * 0x03 is 1-1-1 - * 0x3B is 1-1-2 with 8 dummy clocks - * 0x6B is 1-1-4 with 8 dummy clocks - * 0xBB is 1-2-2 with 4 dummy clocks + * 0x3B is 1-1-2 with 8 clocks + * 0x6B is 1-1-4 with 8 clocks + * 0xBB is 1-2-2 with 4 clocks * Number of IO pins for command * Number of IO pins for address * Number of IO pins for data * Number of bit/bytes for address (3 or 4) - * Number of dummy clocks after address phase + * Number of clocks after address phase */ #ifdef CONFIG_MCHP_QMSPI_TX_DMA int qmspi_transaction_async(const struct spi_device_t *spi_device, @@ -671,7 +671,7 @@ int qmspi_transaction_flush(const struct spi_device_t *spi_device) */ int qmspi_enable(int hw_port, int enable) { - uint8_t dummy __attribute__((unused)) = 0; + uint8_t unused __attribute__((unused)) = 0; trace2(0, QMSPI, 0, "qmspi_enable: port = %d enable = %d", hw_port, enable); @@ -684,13 +684,13 @@ int qmspi_enable(int hw_port, int enable) if (enable) { MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_QMSPI); MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET; - dummy = MCHP_QMSPI0_MODE_ACT_SRST; + unused = MCHP_QMSPI0_MODE_ACT_SRST; MCHP_QMSPI0_MODE = (MCHP_QMSPI_M_ACTIVATE + MCHP_QMSPI_M_SPI_MODE0 + MCHP_QMSPI_M_CLKDIV_12M); } else { MCHP_QMSPI0_MODE_ACT_SRST = MCHP_QMSPI_M_SOFT_RESET; - dummy = MCHP_QMSPI0_MODE_ACT_SRST; + unused = MCHP_QMSPI0_MODE_ACT_SRST; MCHP_QMSPI0_MODE_ACT_SRST = 0; MCHP_PCR_SLP_EN_DEV(MCHP_PCR_QMSPI); } diff --git a/chip/mchp/registers.h b/chip/mchp/registers.h index f7ef36e68c..145e61257d 100644 --- a/chip/mchp/registers.h +++ b/chip/mchp/registers.h @@ -594,7 +594,7 @@ /* MCHP implements 6 GPIO ports */ #define MCHP_GPIO_MAX_PORT (7) -#define DUMMY_GPIO_BANK 0 +#define UNIMPLEMENTED_GPIO_BANK 0 /* * MEC1701 documentation GPIO numbers are octal, each control diff --git a/chip/mchp/util/pack_ec.py b/chip/mchp/util/pack_ec.py index 22a147ed95..4917deee5d 100755 --- a/chip/mchp/util/pack_ec.py +++ b/chip/mchp/util/pack_ec.py @@ -31,10 +31,10 @@ SPI_READ_CMD_LIST = [0x3, 0xb, 0x3b, 0x6b] CRC_TABLE = [0x00, 0x07, 0x0e, 0x09, 0x1c, 0x1b, 0x12, 0x15, 0x38, 0x3f, 0x36, 0x31, 0x24, 0x23, 0x2a, 0x2d] -def dummy_print(*args, **kwargs): +def mock_print(*args, **kwargs): pass -debug_print = dummy_print +debug_print = mock_print def Crc8(crc, data): """Update CRC8 value.""" |