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| author | Jett Rink <jettrink@chromium.org> | 2018-03-22 10:18:49 -0600 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-26 17:03:27 -0700 |
| commit | 6a7fb0d39bf84d7199f0a3f1f9a32cd85dc1113e (patch) | |
| tree | 66ed0813f563bb89527da05dbb1fa884b0e86df7 /chip/mchp | |
| parent | b57ad0e1b82f87e7882e3bd7d05b8e994ad5a414 (diff) | |
| download | chrome-ec-6a7fb0d39bf84d7199f0a3f1f9a32cd85dc1113e.tar.gz | |
lpc: remove lpc_host_reset
No one is using this method and it implies that all chipset should
support the RCIN# Virtual Wire if using eSPI. Only large core chips
use RCIN#; small core chips don't.
This method was introduced for skylake and has since been replaced
since CL:575947 was merged.
BRANCH=none
BUG=none
TEST=build all
Change-Id: Ic541e3d61d1e0ecc64a0bb12385bdada40f0acf2
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/975904
Diffstat (limited to 'chip/mchp')
| -rw-r--r-- | chip/mchp/lpc.c | 18 |
1 files changed, 0 insertions, 18 deletions
diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c index 37c2adc6ac..ac47b042f6 100644 --- a/chip/mchp/lpc.c +++ b/chip/mchp/lpc.c @@ -466,24 +466,6 @@ DECLARE_DEFERRED(lpc_chipset_reset); #endif -#ifdef CONFIG_ESPI -/* - * Called from power/skylake.c chipset_reset() - * For LPC it doesn't call here, instead it pulses RCIN# low for 10 us - */ -void lpc_host_reset(void) -{ - /* Host Reset Control will assert KBRST# (LPC) or RCIN# VW (eSPI) */ -#ifdef CONFIG_ESPI_VW_SIGNALS - espi_vw_pulse_wire(VW_RCIN_L, 0); -#else - gpio_set_level(GPIO_PCH_RCIN_L, 0); - udelay(10); - gpio_set_level(GPIO_PCH_RCIN_L, 1); -#endif -} -#endif /* #ifdef CONFIG_ESPI */ - void lpc_set_init_done(int val) { init_done = val; |