diff options
author | Jett Rink <jettrink@chromium.org> | 2018-05-21 10:22:55 -0600 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-05-22 21:56:39 -0700 |
commit | df06639b1d4fd2798e577f9aead6bc4495d5f3b5 (patch) | |
tree | 060bf073cf3e24c75ffb78aa62855cc28c089c42 /chip/mchp | |
parent | fddf4e703d8673b8ea62f81c8aba3943cfeffea5 (diff) | |
download | chrome-ec-df06639b1d4fd2798e577f9aead6bc4495d5f3b5.tar.gz |
lpc/espi: convert ec chip code to use granular option
Break the ec chip code up with the more granular
CONFIG_HOSTCMD_(X86|LPC|ESPI) options.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067502
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/mchp')
-rw-r--r-- | chip/mchp/build.mk | 4 | ||||
-rw-r--r-- | chip/mchp/clock.c | 4 | ||||
-rw-r--r-- | chip/mchp/config_chip.h | 2 | ||||
-rw-r--r-- | chip/mchp/lpc.c | 14 | ||||
-rw-r--r-- | chip/mchp/lpc_chip.h | 2 | ||||
-rw-r--r-- | chip/mchp/system.c | 2 |
6 files changed, 14 insertions, 14 deletions
diff --git a/chip/mchp/build.mk b/chip/mchp/build.mk index 797ba975e6..c3883a0e6f 100644 --- a/chip/mchp/build.mk +++ b/chip/mchp/build.mk @@ -32,12 +32,12 @@ endif chip-y=clock.o gpio.o hwtimer.o system.o uart.o port80.o tfdp.o chip-$(CONFIG_ADC)+=adc.o chip-$(CONFIG_DMA)+=dma.o -chip-$(CONFIG_ESPI)+=espi.o +chip-$(CONFIG_HOSTCMD_ESPI)+=espi.o chip-$(CONFIG_FANS)+=fan.o chip-$(CONFIG_FLASH_PHYSICAL)+=flash.o chip-$(CONFIG_I2C)+=i2c.o chip-$(CONFIG_MEC_GPIO_EC_CMDS)+=gpio_cmds.o -chip-$(CONFIG_LPC)+=lpc.o +chip-$(CONFIG_HOSTCMD_X86)+=lpc.o chip-$(CONFIG_MCHP_GPSPI)+=gpspi.o chip-$(CONFIG_PWM)+=pwm.o chip-$(CONFIG_SPI)+=spi.o qmspi.o diff --git a/chip/mchp/clock.c b/chip/mchp/clock.c index d0df0240f9..123e26e851 100644 --- a/chip/mchp/clock.c +++ b/chip/mchp/clock.c @@ -358,7 +358,7 @@ static void prepare_for_deep_sleep(void) #endif -#ifdef CONFIG_ESPI +#ifdef CONFIG_HOSTCMD_ESPI #ifdef CONFIG_POWER_S0IX MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI; MCHP_INT_ENABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI; @@ -446,7 +446,7 @@ static void resume_from_deep_sleep(void) */ MCHP_PCR_SLP_EN3 |= (MCHP_PCR_SLP_EN3_HTMR0); -#ifdef CONFIG_ESPI +#ifdef CONFIG_HOSTCMD_ESPI #ifdef CONFIG_POWER_S0IX MCHP_INT_DISABLE(22) = MCHP_INT22_WAKE_ONLY_ESPI; MCHP_INT_SOURCE(22) = MCHP_INT22_WAKE_ONLY_ESPI; diff --git a/chip/mchp/config_chip.h b/chip/mchp/config_chip.h index f69ed386d0..31a895a6d8 100644 --- a/chip/mchp/config_chip.h +++ b/chip/mchp/config_chip.h @@ -121,7 +121,7 @@ /* Optional features present on this chip */ #define CONFIG_ADC #define CONFIG_DMA -#define CONFIG_LPC +#define CONFIG_HOSTCMD_X86 #define CONFIG_SPI #define CONFIG_SWITCH diff --git a/chip/mchp/lpc.c b/chip/mchp/lpc.c index ac47b042f6..3027cfac9a 100644 --- a/chip/mchp/lpc.c +++ b/chip/mchp/lpc.c @@ -85,7 +85,7 @@ static void lpc_generate_smi(void) { /* CPRINTS("LPC Pulse SMI"); */ trace0(0, LPC, 0, "LPC Pulse SMI"); -#ifdef CONFIG_ESPI +#ifdef CONFIG_HOSTCMD_ESPI /* eSPI: pulse SMI# Virtual Wire low */ espi_vw_pulse_wire(VW_SMI_L, 0); #else @@ -104,7 +104,7 @@ static void lpc_generate_sci(void) udelay(65); gpio_set_level(CONFIG_SCI_GPIO, 1); #else -#ifdef CONFIG_ESPI +#ifdef CONFIG_HOSTCMD_ESPI espi_vw_pulse_wire(VW_SCI_L, 0); #else MCHP_ACPI_PM_STS |= 1; @@ -127,7 +127,7 @@ static void lpc_update_wake(host_event_t wake_events) */ wake_events &= ~EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON); -#ifdef CONFIG_ESPI +#ifdef CONFIG_HOSTCMD_ESPI espi_vw_set_wire(VW_WAKE_L, !wake_events); #else /* Signal is asserted low when wake events is non-zero */ @@ -308,7 +308,7 @@ void lpc_mem_mapped_init(void) * For eSPI PLATFORM_RESET# virtual wire is used as LRESET# * */ -#ifndef CONFIG_ESPI +#ifndef CONFIG_HOSTCMD_ESPI static void setup_lpc(void) { gpio_config_module(MODULE_LPC, 1); @@ -425,7 +425,7 @@ static void lpc_init(void) MCHP_PCR_SLP_DIS_DEV(MCHP_PCR_P80CAP0); -#ifdef CONFIG_ESPI +#ifdef CONFIG_HOSTCMD_ESPI espi_init(); @@ -490,7 +490,7 @@ void lpc_set_init_done(int val) */ void lpcrst_interrupt(enum gpio_signal signal) { -#ifndef CONFIG_ESPI +#ifndef CONFIG_HOSTCMD_ESPI /* Initialize LPC module when LRESET# is deasserted */ if (!lpc_get_pltrst_asserted()) { setup_lpc(); @@ -813,7 +813,7 @@ void lpc_clear_acpi_status_mask(uint8_t mask) int lpc_get_pltrst_asserted(void) { -#ifdef CONFIG_ESPI +#ifdef CONFIG_HOSTCMD_ESPI /* * eSPI PLTRST# a VWire or side-band signal * Controlled by CONFIG_ESPI_PLTRST_IS_VWIRE diff --git a/chip/mchp/lpc_chip.h b/chip/mchp/lpc_chip.h index 1961919931..8d4caa3a7c 100644 --- a/chip/mchp/lpc_chip.h +++ b/chip/mchp/lpc_chip.h @@ -8,7 +8,7 @@ #ifndef __CROS_EC_LPC_CHIP_H #define __CROS_EC_LPC_CHIP_H -#ifdef CONFIG_ESPI +#ifdef CONFIG_HOSTCMD_ESPI #include "espi.h" diff --git a/chip/mchp/system.c b/chip/mchp/system.c index 24aafdbf1e..fa844a2304 100644 --- a/chip/mchp/system.c +++ b/chip/mchp/system.c @@ -151,7 +151,7 @@ void system_pre_init(void) MCHP_EC_AHB_ERR = 0; /* write any value to clear */ MCHP_EC_AHB_ERR_EN = 0; /* enable capture of address on error */ -#ifdef CONFIG_ESPI +#ifdef CONFIG_HOSTCMD_ESPI MCHP_EC_GPIO_BANK_PWR |= MCHP_EC_GPIO_BANK_PWR_VTR3_18; #endif |