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| author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 16:07:55 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:42:56 -0700 |
| commit | ac77140b7f4f42075d2377fc9d956a636b05aacf (patch) | |
| tree | c64c6a30916ff741a2ab235141f7bd071cd54483 /chip/mchp | |
| parent | bb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (diff) | |
| download | chrome-ec-ac77140b7f4f42075d2377fc9d956a636b05aacf.tar.gz | |
common: bit change 1 << constants with BIT(constants)
Mechanical replacement of bit operation where operand is a constant.
More bit operation exist, but prone to errors.
Reveal a bug in npcx:
chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow]
BUG=None
BRANCH=None
TEST=None
Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518660
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip/mchp')
| -rw-r--r-- | chip/mchp/gpio.c | 18 | ||||
| -rw-r--r-- | chip/mchp/hwtimer.c | 2 |
2 files changed, 10 insertions, 10 deletions
diff --git a/chip/mchp/gpio.c b/chip/mchp/gpio.c index aa95b8fb0d..eed5c3efbc 100644 --- a/chip/mchp/gpio.c +++ b/chip/mchp/gpio.c @@ -62,7 +62,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) if (func > 0) val |= (func & 0x3) << 12; MCHP_GPIO_CTL(port, i) = val; - mask &= ~(1 << i); + mask &= ~BIT(i); } } @@ -111,7 +111,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) while (mask) { i = GPIO_MASK_TO_NUM(mask); - mask &= ~(1 << i); + mask &= ~BIT(i); val = MCHP_GPIO_CTL(port, i); #ifdef CONFIG_GPIO_POWER_DOWN @@ -191,7 +191,7 @@ void gpio_power_off_by_mask(uint32_t port, uint32_t mask) while (mask) { i = GPIO_MASK_TO_NUM(mask); - mask &= ~(1 << i); + mask &= ~BIT(i); MCHP_GPIO_CTL(port, i) = (MCHP_GPIO_CTRL_PWR_OFF + MCHP_GPIO_INTDET_DISABLED); @@ -235,8 +235,8 @@ int gpio_enable_interrupt(enum gpio_signal signal) port = gpio_list[signal].port; girq_id = int_map[port].girq_id; - MCHP_INT_ENABLE(girq_id) = (1 << i); - MCHP_INT_BLK_EN |= (1 << girq_id); + MCHP_INT_ENABLE(girq_id) = BIT(i); + MCHP_INT_BLK_EN |= BIT(girq_id); return EC_SUCCESS; } @@ -253,7 +253,7 @@ int gpio_disable_interrupt(enum gpio_signal signal) girq_id = int_map[port].girq_id; - MCHP_INT_DISABLE(girq_id) = (1 << i); + MCHP_INT_DISABLE(girq_id) = BIT(i); return EC_SUCCESS; } @@ -291,7 +291,7 @@ int gpio_clear_pending_interrupt(enum gpio_signal signal) girq_id = int_map[port].girq_id; /* Clear interrupt source sticky status bit even if not enabled */ - MCHP_INT_SOURCE(girq_id) = (1 << i); + MCHP_INT_SOURCE(girq_id) = BIT(i); i = MCHP_INT_SOURCE(girq_id); task_clear_pending_irq(girq_id - 8); @@ -394,13 +394,13 @@ static void gpio_interrupt(int girq, int port) bit = __builtin_ffs(g->mask); if (bit) { bit--; - if (sts & (1 << bit)) { + if (sts & BIT(bit)) { trace12(0, GPIO, 0, "Bit[%d]: handler @ 0x%08x", bit, (uint32_t)gpio_irq_handlers[i]); gpio_irq_handlers[i](i); } - sts &= ~(1 << bit); + sts &= ~BIT(bit); } } } diff --git a/chip/mchp/hwtimer.c b/chip/mchp/hwtimer.c index a69fa4ab7e..e84f278f4a 100644 --- a/chip/mchp/hwtimer.c +++ b/chip/mchp/hwtimer.c @@ -115,7 +115,7 @@ int __hw_clock_source_init(uint32_t start_t) MCHP_TMR32_GIRQ_BIT(1); /* * Not needed when using direct mode interrupts - * MCHP_INT_BLK_EN |= (1 << MCHP_TMR32_GIRQ); + * MCHP_INT_BLK_EN |= BIT(MCHP_TMR32_GIRQ); */ return MCHP_IRQ_TIMER32_1; } |