diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2016-04-27 13:54:52 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-04-27 23:58:04 -0700 |
| commit | ab27f42f5636af5fba50a871e391018cb1c885bf (patch) | |
| tree | b3c6e464b0b8e5a44b61c6e814220ef4293b0c92 /chip/mec1322/clock.c | |
| parent | 8d742588ade84d45ce6fe7ca069d6087fac6928c (diff) | |
| download | chrome-ec-ab27f42f5636af5fba50a871e391018cb1c885bf.tar.gz | |
pwm: Add PWM_CONFIG_DSLEEP config flag
Add PWM_CONFIG_DSLEEP PWM config flag, which can be set to keep a
channel active during low-power idle / deep sleep. Currently it's
supported by npcx and mec1322.
BUG=chrome-os-partner:52783
BRANCH=glados
TEST=Manual on chell w/ subsequent commit + CONFIG_LOW_POWER_S0. Verify
KB backlight does not flicker during idle.
Change-Id: Ib9df5879aaa7dfa5764de1583496de84d40d2bb5
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/341002
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Diffstat (limited to 'chip/mec1322/clock.c')
| -rw-r--r-- | chip/mec1322/clock.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c index 6a1674891e..a49d2362aa 100644 --- a/chip/mec1322/clock.c +++ b/chip/mec1322/clock.c @@ -11,6 +11,8 @@ #include "cpu.h" #include "hooks.h" #include "hwtimer.h" +#include "pwm.h" +#include "pwm_chip.h" #include "registers.h" #include "shared_mem.h" #include "system.h" @@ -181,6 +183,9 @@ static void system_reset_htimer_alarm(void) */ static void prepare_for_deep_sleep(void) { + uint32_t ec_slp_en = MEC1322_PCR_EC_SLP_EN | + MEC1322_PCR_EC_SLP_EN_SLEEP; + /* sysTick timer */ CPU_NVIC_ST_CTRL &= ~ST_ENABLE; CPU_NVIC_ST_CTRL &= ~ST_COUNTFLAG; @@ -199,14 +204,21 @@ static void prepare_for_deep_sleep(void) MEC1322_TMR16_CTL(0) &= ~1; MEC1322_PCR_CHIP_SLP_EN |= 0x3; - MEC1322_PCR_EC_SLP_EN |= MEC1322_PCR_EC_SLP_EN_SLEEP; +#ifdef CONFIG_PWM + if (pwm_get_keep_awake_mask()) + ec_slp_en &= ~pwm_get_keep_awake_mask(); + else +#endif + /* Disable 100 Khz clock */ + MEC1322_PCR_SLOW_CLK_CTL &= 0xFFFFFC00; + + MEC1322_PCR_EC_SLP_EN = ec_slp_en; MEC1322_PCR_HOST_SLP_EN |= MEC1322_PCR_HOST_SLP_EN_SLEEP; MEC1322_PCR_EC_SLP_EN2 |= MEC1322_PCR_EC_SLP_EN2_SLEEP; #ifndef CONFIG_POWER_S0IX MEC1322_LPC_ACT = 0x0; #endif - MEC1322_PCR_SLOW_CLK_CTL &= 0xFFFFFC00; MEC1322_PCR_SYS_SLP_CTL = 0x2; /* heavysleep 2 */ @@ -242,8 +254,6 @@ static void resume_from_deep_sleep(void) /* Enable LPC */ MEC1322_LPC_ACT |= 1; #endif - - MEC1322_PCR_SLOW_CLK_CTL = 0x1E0; } |