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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-07 13:47:48 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-16 14:49:32 -0700 |
| commit | 1167cad6a88e45bbf6a5599f19d018cd6a8b5233 (patch) | |
| tree | eaff44a061fa989b49a5c52fc58ef14f3ccb48c3 /chip/mec1322/config_flash_layout.h | |
| parent | 558c465165acf494905fa59c822c7190b4646899 (diff) | |
| download | chrome-ec-1167cad6a88e45bbf6a5599f19d018cd6a8b5233.tar.gz | |
cleanup: Change meaning of storage offset CONFIGs
In order to support architectures with non-contiguous writable and
protected regions, change storage offsets to be relative to writable and
protected regions, rather than relative to "the start of the region of
storage belonging to the EC".
Spec doc available at https://goo.gl/fnzTvr.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I796f8e7305a6336495bd256a78774595cb16a2e4
Reviewed-on: https://chromium-review.googlesource.com/297823
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/mec1322/config_flash_layout.h')
| -rw-r--r-- | chip/mec1322/config_flash_layout.h | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h index 0efa9d8345..6b037df6d0 100644 --- a/chip/mec1322/config_flash_layout.h +++ b/chip/mec1322/config_flash_layout.h @@ -20,13 +20,19 @@ #undef CONFIG_FLASH_PSTATE #define CONFIG_SPI_FLASH -/* Size of SPI memory used by EC (lfw + RSA Keys + RO + RW + boot header) */ -#define CONFIG_FLASH_BASE_SPI (CONFIG_SPI_FLASH_SIZE - (0x40000)) +/* EC region of SPI resides at end of ROM, protected region follows writable */ +#define CONFIG_EC_PROTECTED_STORAGE_OFF (CONFIG_SPI_FLASH_SIZE - 0x20000) +#define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x20000 +#define CONFIG_EC_WRITABLE_STORAGE_OFF (CONFIG_SPI_FLASH_SIZE - 0x40000) +#define CONFIG_EC_WRITABLE_STORAGE_SIZE 0x20000 + /* Size of one firmware image in flash */ #ifndef CONFIG_FW_IMAGE_SIZE #define CONFIG_FW_IMAGE_SIZE (96 * 1024) #endif +/* redundant..*/ +#define CONFIG_FLASH_PHYSICAL_SIZE CONFIG_SPI_FLASH_SIZE #define CONFIG_FLASH_SIZE CONFIG_FLASH_PHYSICAL_SIZE /* Loader resides at the beginning of program memory */ @@ -34,12 +40,12 @@ #define CONFIG_LOADER_SIZE 0x1000 /* Write protect Loader and RO Image */ -#define CONFIG_WP_OFF (CONFIG_FLASH_PHYSICAL_SIZE >> 1) +#define CONFIG_WP_STORAGE_OFF CONFIG_EC_PROTECTED_STORAGE_OFF /* * Write protect 128k section of 256k physical flash which contains loader * and RO Images. */ -#define CONFIG_WP_SIZE (CONFIG_FLASH_PHYSICAL_SIZE >> 1) +#define CONFIG_WP_STORAGE_SIZE CONFIG_EC_PROTECTED_STORAGE_SIZE /* * RO / RW images follow the loader in program memory. Either RO or RW @@ -52,7 +58,7 @@ #define CONFIG_RW_SIZE CONFIG_RO_SIZE /* WP region consists of second half of SPI, and begins with the boot header */ -#define CONFIG_BOOT_HEADER_STORAGE_OFF CONFIG_WP_OFF +#define CONFIG_BOOT_HEADER_STORAGE_OFF 0 #define CONFIG_BOOT_HEADER_STORAGE_SIZE 0x240 /* Loader / lfw image immediately follows the boot header on SPI */ @@ -66,9 +72,4 @@ /* RW image starts at the beginning of SPI */ #define CONFIG_RW_STORAGE_OFF 0 -#define CONFIG_RO_IMAGE_FLASHADDR (CONFIG_FLASH_BASE_SPI + \ - CONFIG_RO_STORAGE_OFF) -#define CONFIG_RW_IMAGE_FLASHADDR (CONFIG_FLASH_BASE_SPI + \ - CONFIG_RW_STORAGE_OFF) - #endif /* __CROS_EC_CONFIG_FLASH_LAYOUT_H */ |