diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2016-01-15 16:48:40 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-01-19 14:24:39 -0800 |
| commit | e933d0b7b6984bc8abf40b3364695d9955a9a426 (patch) | |
| tree | 83fc07a010d899fd3427522850f2ee5d10eaeccb /chip/mec1322/lpc.c | |
| parent | c21a0b8083506e7f824c7829043ff1978b389a09 (diff) | |
| download | chrome-ec-e933d0b7b6984bc8abf40b3364695d9955a9a426.tar.gz | |
mec1322: lpc: Clear STATUS_PROCESSING LPC status bit on init
When a sysjump host command is received, there is a (usually) small
period of time when the EC has sent a reply packet back to the host, but
interrupts are still enabled. If the host sends a new host command,
STATUS_PROCESSING will be set by the EC ISR, but the host command will
never be handled due to pending sysjump. In this case, STATUS_PROCESSING
will still be set, so we need to clear it on LPC post-sysjump re-init.
BUG=chrome-os-partner:49318
TEST=Add 200ms msleep before call to interrupt_disable() in
jump_to_image(), boot to software sync, and verify host commands are
handled successfully post-sysjump and system continues to boot.
BRANCH=glados, cyan
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Id0878df738541f7d5d158821a68988a8e6dc6759
Reviewed-on: https://chromium-review.googlesource.com/322431
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'chip/mec1322/lpc.c')
| -rw-r--r-- | chip/mec1322/lpc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index e5e86b4454..32d04036de 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -229,12 +229,15 @@ static void setup_lpc(void) MEC1322_LPC_ACPI_EC0_BAR = 0x00628304; MEC1322_INT_ENABLE(15) |= 1 << 6; MEC1322_INT_BLK_EN |= 1 << 15; + /* Clear STATUS_PROCESSING bit in case it was set during sysjump */ + MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING; task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); /* Set up ACPI1 for 0x200/0x204 */ MEC1322_LPC_ACPI_EC1_BAR = 0x02008407; MEC1322_INT_ENABLE(15) |= 1 << 8; MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; task_enable_irq(MEC1322_IRQ_ACPIEC1_IBF); /* Set up 8042 interface at 0x60/0x64 */ |