mec1322: i2c: Support multiple I2C ports on the same controller

mec1322 I2C controller 0 has two attached ports. Modify the I2C driver so
that both ports are usable.

BUG=chrome-os-partner:38335,chrome-os-partner:38945
TEST=Manual on strago. Verify that i2cscan is functional.
BRANCH=None

Change-Id: I18d9d516984d041a38c86fd4ec1b0bfa4e885c9f
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/265951
Reviewed-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-by: Alec Berg <alecaberg@chromium.org>

1 files changed, 38 insertions, 25 deletions

diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h
index ca06cb25f5..af89609dc9 100644
--- a/chip/mec1322/registers.h
+++ b/chip/mec1322/registers.h
@@ -245,31 +245,44 @@ static inline uintptr_t gpio_port_base(int port_id)
 #define MEC1322_I2C2_BASE      0x4000b000
 #define MEC1322_I2C3_BASE      0x4000b400
 #define MEC1322_I2C_BASESEP    0x00000400
-#define MEC1322_I2C_ADDR(port, offset) \
-	(offset + (port == 0 ? MEC1322_I2C0_BASE : \
-		   MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (port - 1)))
-
-#define MEC1322_I2C_CTRL(port)          REG8(MEC1322_I2C_ADDR(port, 0x0))
-#define MEC1322_I2C_STATUS(port)        REG8(MEC1322_I2C_ADDR(port, 0x0))
-#define MEC1322_I2C_OWN_ADDR(port)      REG16(MEC1322_I2C_ADDR(port, 0x4))
-#define MEC1322_I2C_DATA(port)          REG8(MEC1322_I2C_ADDR(port, 0x8))
-#define MEC1322_I2C_MASTER_CMD(port)    REG32(MEC1322_I2C_ADDR(port, 0xc))
-#define MEC1322_I2C_SLAVE_CMD(port)     REG32(MEC1322_I2C_ADDR(port, 0x10))
-#define MEC1322_I2C_PEC(port)           REG8(MEC1322_I2C_ADDR(port, 0x14))
-#define MEC1322_I2C_DATA_TIM_2(port)    REG8(MEC1322_I2C_ADDR(port, 0x18))
-#define MEC1322_I2C_COMPLETE(port)      REG32(MEC1322_I2C_ADDR(port, 0x20))
-#define MEC1322_I2C_IDLE_SCALE(port)    REG32(MEC1322_I2C_ADDR(port, 0x24))
-#define MEC1322_I2C_CONFIG(port)        REG32(MEC1322_I2C_ADDR(port, 0x28))
-#define MEC1322_I2C_BUS_CLK(port)       REG16(MEC1322_I2C_ADDR(port, 0x2c))
-#define MEC1322_I2C_BLK_ID(port)        REG8(MEC1322_I2C_ADDR(port, 0x30))
-#define MEC1322_I2C_REV(port)           REG8(MEC1322_I2C_ADDR(port, 0x34))
-#define MEC1322_I2C_BB_CTRL(port)       REG8(MEC1322_I2C_ADDR(port, 0x38))
-#define MEC1322_I2C_DATA_TIM(port)      REG32(MEC1322_I2C_ADDR(port, 0x40))
-#define MEC1322_I2C_TOUT_SCALE(port)    REG32(MEC1322_I2C_ADDR(port, 0x44))
-#define MEC1322_I2C_SLAVE_TX_BUF(port)  REG8(MEC1322_I2C_ADDR(port, 0x48))
-#define MEC1322_I2C_SLAVE_RX_BUF(port)  REG8(MEC1322_I2C_ADDR(port, 0x4c))
-#define MEC1322_I2C_MASTER_TX_BUF(port) REG8(MEC1322_I2C_ADDR(port, 0x50))
-#define MEC1322_I2C_MASTER_RX_BUF(port) REG8(MEC1322_I2C_ADDR(port, 0x54))
+#define MEC1322_I2C_ADDR(controller, offset) \
+	(offset + (controller == 0 ? MEC1322_I2C0_BASE : \
+		   MEC1322_I2C1_BASE + MEC1322_I2C_BASESEP * (controller - 1)))
+
+/*
+ * MEC1322 has five ports distributed among four controllers. Locking must
+ * occur by-controller (not by-port).
+ */
+enum mec1322_i2c_port {
+	MEC1322_I2C0_0 = 0,      /* Controller 0, port 0 */
+	MEC1322_I2C0_1 = 1,      /* Controller 0, port 1 */
+	MEC1322_I2C1   = 2,      /* Controller 1 */
+	MEC1322_I2C2   = 3,      /* Controller 2 */
+	MEC1322_I2C3   = 4,      /* Controller 3 */
+	MEC1322_I2C_PORT_COUNT,
+};
+
+#define MEC1322_I2C_CTRL(ctrl)          REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
+#define MEC1322_I2C_STATUS(ctrl)        REG8(MEC1322_I2C_ADDR(ctrl, 0x0))
+#define MEC1322_I2C_OWN_ADDR(ctrl)      REG16(MEC1322_I2C_ADDR(ctrl, 0x4))
+#define MEC1322_I2C_DATA(ctrl)          REG8(MEC1322_I2C_ADDR(ctrl, 0x8))
+#define MEC1322_I2C_MASTER_CMD(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0xc))
+#define MEC1322_I2C_SLAVE_CMD(ctrl)     REG32(MEC1322_I2C_ADDR(ctrl, 0x10))
+#define MEC1322_I2C_PEC(ctrl)           REG8(MEC1322_I2C_ADDR(ctrl, 0x14))
+#define MEC1322_I2C_DATA_TIM_2(ctrl)    REG8(MEC1322_I2C_ADDR(ctrl, 0x18))
+#define MEC1322_I2C_COMPLETE(ctrl)      REG32(MEC1322_I2C_ADDR(ctrl, 0x20))
+#define MEC1322_I2C_IDLE_SCALE(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0x24))
+#define MEC1322_I2C_CONFIG(ctrl)        REG32(MEC1322_I2C_ADDR(ctrl, 0x28))
+#define MEC1322_I2C_BUS_CLK(ctrl)       REG16(MEC1322_I2C_ADDR(ctrl, 0x2c))
+#define MEC1322_I2C_BLK_ID(ctrl)        REG8(MEC1322_I2C_ADDR(ctrl, 0x30))
+#define MEC1322_I2C_REV(ctrl)           REG8(MEC1322_I2C_ADDR(ctrl, 0x34))
+#define MEC1322_I2C_BB_CTRL(ctrl)       REG8(MEC1322_I2C_ADDR(ctrl, 0x38))
+#define MEC1322_I2C_DATA_TIM(ctrl)      REG32(MEC1322_I2C_ADDR(ctrl, 0x40))
+#define MEC1322_I2C_TOUT_SCALE(ctrl)    REG32(MEC1322_I2C_ADDR(ctrl, 0x44))
+#define MEC1322_I2C_SLAVE_TX_BUF(ctrl)  REG8(MEC1322_I2C_ADDR(ctrl, 0x48))
+#define MEC1322_I2C_SLAVE_RX_BUF(ctrl)  REG8(MEC1322_I2C_ADDR(ctrl, 0x4c))
+#define MEC1322_I2C_MASTER_TX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x50))
+#define MEC1322_I2C_MASTER_RX_BUF(ctrl) REG8(MEC1322_I2C_ADDR(ctrl, 0x54))
 
 
 /* Keyboard scan matrix */