diff options
| author | Vic (Chun-Ju) Yang <victoryang@chromium.org> | 2014-01-09 11:53:17 +0800 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-01-09 20:25:18 +0000 |
| commit | b6f8f36aa426b84d673464a15b37df669ecad57c (patch) | |
| tree | b11057afeb7954f476e0f2a9aadd00c1516f253b /chip/mec1322/registers.h | |
| parent | 72481572aad731b3c2db20c41efb6d5a51812eaa (diff) | |
| download | chrome-ec-b6f8f36aa426b84d673464a15b37df669ecad57c.tar.gz | |
mec1322: Use internal SCI pin control
Instead of requiring a GPIO definition, default to using the internal
SCI pin control.
BUG=chrome-os-partner:24550
TEST=Trigger SCI and verify with logic analyzer
BRANCH=None
Change-Id: I13ac3b8f1031d3c56ea0b8f6a6ed0c1aa4e77bb1
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182010
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/mec1322/registers.h')
| -rw-r--r-- | chip/mec1322/registers.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h index 5a5aa98f2b..47a839ed96 100644 --- a/chip/mec1322/registers.h +++ b/chip/mec1322/registers.h @@ -190,6 +190,18 @@ static inline uintptr_t gpio_port_base(int port_id) #define MEC1322_ACPI_EC_BYTE_CTL(x) REG8(MEC1322_ACPI_EC_BASE(x) + 0x105) #define MEC1322_ACPI_EC_OS2EC(x, y) REG8(MEC1322_ACPI_EC_BASE(x) + 0x108 + (y)) +#define MEC1322_ACPI_PM_RT_BASE 0x400f1400 +#define MEC1322_ACPI_PM1_STS1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x0) +#define MEC1322_ACPI_PM1_STS2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x1) +#define MEC1322_ACPI_PM1_EN1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x2) +#define MEC1322_ACPI_PM1_EN2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x3) +#define MEC1322_ACPI_PM1_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x4) +#define MEC1322_ACPI_PM1_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x5) +#define MEC1322_ACPI_PM2_CTL1 REG8(MEC1322_ACPI_PM_RT_BASE + 0x6) +#define MEC1322_ACPI_PM2_CTL2 REG8(MEC1322_ACPI_PM_RT_BASE + 0x7) +#define MEC1322_ACPI_PM_EC_BASE 0x400f1500 +#define MEC1322_ACPI_PM_STS REG8(MEC1322_ACPI_PM_EC_BASE + 0x10) + /* 8042 */ #define MEC1322_8042_BASE 0x400f0400 |