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authorDivya Jyothi <divya.jyothi@intel.com>2015-05-14 10:11:13 -0700
committerChromeOS Commit Bot <chromeos-commit-bot@chromium.org>2015-06-14 22:18:34 +0000
commitb99f00b7f974faec2329f21100f72e0a332be1f2 (patch)
treec7602436bf5724e9dc841edb12caca752339c017 /chip/mec1322/registers.h
parent5ea69a7b3b06d8877fc0d420a6892b1db42cd290 (diff)
downloadchrome-ec-b99f00b7f974faec2329f21100f72e0a332be1f2.tar.gz
mec1322: Added support for sysjump.stabilize-7173.B
changes added to support flashrom are: sysjump support to be able to copy the RO/RW image and jump to it without causing AP to reboot while its alreday ON. LPC init should be reinitialized on sysjump corrected gpio_set_flags_by_mask to make sure we update the register only for GPIO_LOW condition and not all else conditions. BUG=chrome-os-partner:38103 TEST=commands : flashrom -p ec -w ec.bin flashrom -p ec -r ec.bin BRANCH=none Change-Id: I23892f0378d756052030e73034c3acdd41477e34 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/272000 Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/mec1322/registers.h')
-rw-r--r--chip/mec1322/registers.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h
index 1c21e9b8bf..b7a8612f83 100644
--- a/chip/mec1322/registers.h
+++ b/chip/mec1322/registers.h
@@ -130,6 +130,11 @@ static inline uintptr_t gpio_port_base(int port_id)
#define MEC1322_VBAT_CE REG32(MEC1322_VBAT_BASE + 0x8)
#define MEC1322_VBAT_RAM(x) REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x))
+/* Miscellaneous firmware control fields
+ * scratch pad index cannot be more than 16 as
+ * mec has 64 bytes = 16 indexes of scratchpad RAM
+ */
+#define MEC1322_IMAGETYPE_IDX 15
/* LPC */
#define MEC1322_LPC_CFG_BASE 0x400f3300