diff options
| author | Steven Jian <steven.jian@intel.com> | 2015-04-01 01:25:42 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-27 03:58:16 +0000 |
| commit | 937cc8a64e5971def21303e7a19a4ad9553e0ace (patch) | |
| tree | 321543152e0c4d61e686ca7b92edd0d027bb168b /chip/mec1322/registers.h | |
| parent | e216906c9327655d71b8758b7f11c2f744e55018 (diff) | |
| download | chrome-ec-937cc8a64e5971def21303e7a19a4ad9553e0ace.tar.gz | |
mec1322: Simplify GPIO lists
Our existing GPIO macros use port# / gpio#, but the concept of different
GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros
for chips which do not have distinct GPIO ports.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b
Signed-off-by: Steven Jian <steven.jian@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/262841
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Diffstat (limited to 'chip/mec1322/registers.h')
| -rw-r--r-- | chip/mec1322/registers.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h index 88b055eaa5..1c21e9b8bf 100644 --- a/chip/mec1322/registers.h +++ b/chip/mec1322/registers.h @@ -89,8 +89,7 @@ /* GPIO */ #define MEC1322_GPIO_BASE 0x40081000 -#define MEC1322_GPIO_PORT(x) (x) -#define GPIO_PORT(x) MEC1322_GPIO_PORT(x) + static inline uintptr_t gpio_port_base(int port_id) { int oct = (port_id / 10) * 8 + port_id % 10; @@ -98,7 +97,7 @@ static inline uintptr_t gpio_port_base(int port_id) } #define MEC1322_GPIO_CTL(port, id) REG32(gpio_port_base(port) + (id << 2)) -#define DUMMY_GPIO_BANK GPIO_PORT(0) +#define DUMMY_GPIO_BANK 0 /* Timer */ |