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authorShamile Khan <shamile.khan@intel.com>2015-10-06 10:02:42 -0700
committerchrome-bot <chrome-bot@chromium.org>2015-10-07 22:19:34 -0700
commit7e07e469f35f80337d9bb5c8767a9a35aa348b55 (patch)
tree6b37b78dc125ee95345d44c9cf16af5942c69b65 /chip/mec1322/system.c
parente05fcfcfe7aa4bcc5d0e4288e5b67e32f83fc2af (diff)
downloadchrome-ec-7e07e469f35f80337d9bb5c8767a9a35aa348b55.tar.gz
mec1322: Do not set mux mode to GPIO in gpio_set_flags_by_mask()
gpio_set_flags_by_mask() should only set the GPIO flags for a pin. gpio_set_alternate_function() should set all mux modes including GPIO mode for a pin. This bug was uncovered when a glitch was observed on EC's LRESET# pin which reset the LPC bus. The glitch was caused when the LPC interface was re-initialized during execution of EC RW image. While programming the EC pins for LPC interface, LRESET# pin was temporarily converted from LRESET# mode to GPIO mode by gpio_set_flags_by_mask() before it got set back to LRESET# mode by gpio_set_alternate_function() BUG=chrome-os-partner:44993 BRANCH=none TEST=Manually tested on Kunimitsu FAB3. Flashed a coreboot image in which LPC SERIRQ is set to quiet mode and Clock Run is enabled and than confirmed that keyboard is functional. Change-Id: I25865d38bd6b6b5785e4247831722c5a02032138 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/304146 Reviewed-by: Shawn N <shawnn@chromium.org>
Diffstat (limited to 'chip/mec1322/system.c')
-rw-r--r--chip/mec1322/system.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
index 071cb96e80..d97f5b0c4e 100644
--- a/chip/mec1322/system.c
+++ b/chip/mec1322/system.c
@@ -251,6 +251,7 @@ static void system_set_gpio_power(int enabled, uint32_t *backup_gpio_ctl)
backup_gpio_ctl[i * 8 + j] =
MEC1322_GPIO_CTL(port, j);
gpio_set_flags_by_mask(port, 1 << j, flags);
+ gpio_set_alternate_function(port, 1 << j, -1);
}
}
}
@@ -357,6 +358,8 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds)
gpio_set_flags_by_mask(gpio_list[*pin].port,
gpio_list[*pin].mask,
gpio_list[*pin].flags);
+ gpio_set_alternate_function(gpio_list[*pin].port,
+ gpio_list[*pin].mask, -1);
gpio_enable_interrupt(*pin);
}