mec1322: improve UART Tx performance

On MEC1322, we don't have indication of empty space in transmit FIFO. To
work around this, we needed to look at Tx FIFO empty bit instead. However,
this effectively made the FIFO length one. This CL fixes this by only
checking Tx FIFO empty bit every 16 characters written to Tx FIFO. This
is assuming the UART module works the same way as 16550 UART, which has
a 16-byte FIFO.

In a simple bulk write test, this improves Tx performance by 30%.

BUG=chrome-os-partner:24107
TEST=Build and boot. Check console still works.
BRANCH=None

Change-Id: I97a6f42bd11be6bb18bc339af6d9b0cf2bae4845
Signed-off-by: Vic Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/206160
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>

1 files changed, 7 insertions, 3 deletions

diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c
index 00865c841b..fe47ee262d 100644
--- a/chip/mec1322/uart.c
+++ b/chip/mec1322/uart.c
@@ -16,7 +16,10 @@
 #include "uart.h"
 #include "util.h"
 
+#define TX_FIFO_SIZE 16
+
 static int init_done;
+static int tx_fifo_used;
 
 int uart_init_done(void)
 {
@@ -54,10 +57,10 @@ void uart_tx_flush(void)
 int uart_tx_ready(void)
 {
 	/*
-	 * TODO(crosbug.com/p/24107): This is FIFO empty bit instead of
-	 *                            FIFO full bit?
+	 * We have no indication of free space in transmit FIFO. To work around
+	 * this, we check transmit FIFO empty bit every 16 characters written.
 	 */
-	return MEC1322_UART_LSR & (1 << 5);
+	return tx_fifo_used != 0 || MEC1322_UART_LSR & (1 << 5);
 }
 
 int uart_rx_available(void)
@@ -71,6 +74,7 @@ void uart_write_char(char c)
 	while (!uart_tx_ready())
 		;
 
+	tx_fifo_used = (tx_fifo_used + 1) % TX_FIFO_SIZE;
 	MEC1322_UART_TB = c;
 }