diff options
| author | Jack Rosenthal <jrosenth@chromium.org> | 2022-06-27 14:20:41 -0600 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-30 18:49:23 +0000 |
| commit | 3c680b65f04f70a39a14e4d7cd8037bad64037cc (patch) | |
| tree | 333da94f94102e2f196827998550a701922fd9e3 /chip/mec1322 | |
| parent | 902109ba45220d5d0defce4890160bdb4dbce50a (diff) | |
| download | chrome-ec-3c680b65f04f70a39a14e4d7cd8037bad64037cc.tar.gz | |
chip/mec1322/config_chip.h: Format with clang-format
BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: I6becce210abfaca4da53e2e9e76df09af30b09f1
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729306
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Diffstat (limited to 'chip/mec1322')
| -rw-r--r-- | chip/mec1322/config_chip.h | 55 |
1 files changed, 27 insertions, 28 deletions
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h index 951de3fb4f..4d61174e68 100644 --- a/chip/mec1322/config_chip.h +++ b/chip/mec1322/config_chip.h @@ -10,15 +10,15 @@ #include "core/cortex-m/config_core.h" /* Number of IRQ vectors on the NVIC */ -#define CONFIG_IRQ_COUNT 93 +#define CONFIG_IRQ_COUNT 93 /* Use a bigger console output buffer */ #undef CONFIG_UART_TX_BUF_SIZE -#define CONFIG_UART_TX_BUF_SIZE 2048 +#define CONFIG_UART_TX_BUF_SIZE 2048 /* Interval between HOOK_TICK notifications */ -#define HOOK_TICK_INTERVAL_MS 250 -#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) +#define HOOK_TICK_INTERVAL_MS 250 +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) /* * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one @@ -26,8 +26,8 @@ */ #define CONFIG_I2C_MULTI_PORT_CONTROLLER -#define I2C_CONTROLLER_COUNT 4 -#define I2C_PORT_COUNT 5 +#define I2C_CONTROLLER_COUNT 4 +#define I2C_PORT_COUNT 5 /****************************************************************************/ /* Memory mapping */ @@ -45,52 +45,51 @@ /****************************************************************************/ /* Define our RAM layout. */ -#define CONFIG_MEC_SRAM_BASE_START 0x00100000 -#define CONFIG_MEC_SRAM_BASE_END 0x00120000 -#define CONFIG_MEC_SRAM_SIZE (CONFIG_MEC_SRAM_BASE_END - \ - CONFIG_MEC_SRAM_BASE_START) +#define CONFIG_MEC_SRAM_BASE_START 0x00100000 +#define CONFIG_MEC_SRAM_BASE_END 0x00120000 +#define CONFIG_MEC_SRAM_SIZE \ + (CONFIG_MEC_SRAM_BASE_END - CONFIG_MEC_SRAM_BASE_START) /* 20k RAM for RO / RW / loader */ -#define CONFIG_RAM_SIZE 0x00005000 -#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - \ - CONFIG_RAM_SIZE) +#define CONFIG_RAM_SIZE 0x00005000 +#define CONFIG_RAM_BASE (CONFIG_MEC_SRAM_BASE_END - CONFIG_RAM_SIZE) /* System stack size */ -#define CONFIG_STACK_SIZE 1024 +#define CONFIG_STACK_SIZE 1024 /* non-standard task stack sizes */ -#define IDLE_TASK_STACK_SIZE 512 -#define LARGER_TASK_STACK_SIZE 640 +#define IDLE_TASK_STACK_SIZE 512 +#define LARGER_TASK_STACK_SIZE 640 -#define CHARGER_TASK_STACK_SIZE 640 -#define HOOKS_TASK_STACK_SIZE 640 -#define CONSOLE_TASK_STACK_SIZE 640 -#define HOST_CMD_TASK_STACK_SIZE 640 +#define CHARGER_TASK_STACK_SIZE 640 +#define HOOKS_TASK_STACK_SIZE 640 +#define CONSOLE_TASK_STACK_SIZE 640 +#define HOST_CMD_TASK_STACK_SIZE 640 /* * TODO: Large stack consumption * https://code.google.com/p/chrome-os-partner/issues/detail?id=49245 */ -#define PD_TASK_STACK_SIZE 800 +#define PD_TASK_STACK_SIZE 800 /* Default task stack size */ -#define TASK_STACK_SIZE 512 +#define TASK_STACK_SIZE 512 /****************************************************************************/ /* Define our flash layout. */ /* Protect bank size 4K bytes */ -#define CONFIG_FLASH_BANK_SIZE 0x00001000 +#define CONFIG_FLASH_BANK_SIZE 0x00001000 /* Sector erase size 4K bytes */ -#define CONFIG_FLASH_ERASE_SIZE 0x00001000 +#define CONFIG_FLASH_ERASE_SIZE 0x00001000 /* Minimum write size */ -#define CONFIG_FLASH_WRITE_SIZE 0x00000004 +#define CONFIG_FLASH_WRITE_SIZE 0x00000004 /* One page size for write */ -#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 +#define CONFIG_FLASH_WRITE_IDEAL_SIZE 256 /* Program memory base address */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 +#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000 #include "config_flash_layout.h" @@ -110,4 +109,4 @@ #define GPIO_PIN(index) (index / 10), (1 << (index % 10)) #define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) -#endif /* __CROS_EC_CONFIG_CHIP_H */ +#endif /* __CROS_EC_CONFIG_CHIP_H */ |