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authorShawn Nematbakhsh <shawnn@chromium.org>2015-09-04 19:09:33 -0700
committerchrome-bot <chrome-bot@chromium.org>2015-09-16 14:49:31 -0700
commitd58e54730c03290296df5bb65cb84264e4b2facc (patch)
treed736570c84a0e9737b8881ec68b073327a5c2ae5 /chip/mec1322
parent4b3c13ddfefd229dde49fb4cbf5a6bfc49f64973 (diff)
downloadchrome-ec-d58e54730c03290296df5bb65cb84264e4b2facc.tar.gz
cleanup: Rename geometry constants
Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/mec1322')
-rw-r--r--chip/mec1322/config_chip.h4
-rw-r--r--chip/mec1322/config_flash_layout.h3
-rw-r--r--chip/mec1322/lfw/ec_lfw.c7
-rw-r--r--chip/mec1322/system.c3
4 files changed, 9 insertions, 8 deletions
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
index f668765482..514f292914 100644
--- a/chip/mec1322/config_chip.h
+++ b/chip/mec1322/config_chip.h
@@ -99,10 +99,8 @@
#define CONFIG_FLASH_PHYSICAL_SIZE 0x00040000
/* Program memory base address */
-#define CONFIG_FLASH_BASE 0x00100000
-
+#define CONFIG_PROGRAM_MEMORY_BASE 0x00100000
#define CONFIG_CDRAM_BASE 0x00100000
-#define CONFIG_CDRAM_SIZE 0x00020000
#include "config_flash_layout.h"
diff --git a/chip/mec1322/config_flash_layout.h b/chip/mec1322/config_flash_layout.h
index d7a16085c9..4a10175a02 100644
--- a/chip/mec1322/config_flash_layout.h
+++ b/chip/mec1322/config_flash_layout.h
@@ -16,7 +16,8 @@
/* Non-memmapped, external SPI */
#define CONFIG_CODERAM_ARCH
-#undef CONFIG_FLASH_MAPPED
+#define CONFIG_EXTERNAL_STORAGE
+#undef CONFIG_MAPPED_STORAGE
#undef CONFIG_FLASH_PSTATE
#define CONFIG_SPI_FLASH
diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c
index 1e48cb25da..db02a7df57 100644
--- a/chip/mec1322/lfw/ec_lfw.c
+++ b/chip/mec1322/lfw/ec_lfw.c
@@ -91,7 +91,8 @@ static int spi_flash_readloc(uint8_t *buf_usr,
int spi_image_load(uint32_t offset)
{
- uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF + CONFIG_FLASH_BASE);
+ uint8_t *buf = (uint8_t *) (CONFIG_RW_MEM_OFF +
+ CONFIG_PROGRAM_MEMORY_BASE);
uint32_t i;
memset((void *)buf, 0xFF, (CONFIG_FW_IMAGE_SIZE - 4));
@@ -257,7 +258,7 @@ void lfw_main()
switch (system_get_image_copy()) {
case SYSTEM_IMAGE_RW:
uart_puts("lfw-RW load\n");
- init_addr = CONFIG_RW_MEM_OFF + CONFIG_FLASH_BASE;
+ init_addr = CONFIG_RW_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
spi_image_load(CONFIG_RW_IMAGE_FLASHADDR);
break;
case SYSTEM_IMAGE_RO:
@@ -267,7 +268,7 @@ void lfw_main()
default:
MEC1322_VBAT_RAM(MEC1322_IMAGETYPE_IDX) =
SYSTEM_IMAGE_RO;
- init_addr = CONFIG_RO_MEM_OFF + CONFIG_FLASH_BASE;
+ init_addr = CONFIG_RO_MEM_OFF + CONFIG_PROGRAM_MEMORY_BASE;
}
jump_to_image(*(uintptr_t *)(init_addr + 4));
diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c
index ce25c87620..fd8c79a2f1 100644
--- a/chip/mec1322/system.c
+++ b/chip/mec1322/system.c
@@ -448,7 +448,8 @@ enum system_image_copy_t system_get_shrspi_image_copy(void)
uint32_t system_get_lfw_address(void)
{
- uint32_t * const lfw_vector = (uint32_t * const) CONFIG_FLASH_BASE;
+ uint32_t * const lfw_vector =
+ (uint32_t * const)CONFIG_PROGRAM_MEMORY_BASE;
return *(lfw_vector + 1);
}