diff options
author | Gwendal Grignou <gwendal@chromium.org> | 2019-03-11 15:57:52 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-26 04:42:55 -0700 |
commit | bb266fc26fc05d4ab22de6ad7bce5b477c9f9140 (patch) | |
tree | f6ada087f62246c3a9547e649ac8846b0ed6d5ab /chip/mec1322 | |
parent | 0bfc511527cf2aebfa163c63a1d028419ca0b0c3 (diff) | |
download | chrome-ec-bb266fc26fc05d4ab22de6ad7bce5b477c9f9140.tar.gz |
common: replace 1 << digits, with BIT(digits)
Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Diffstat (limited to 'chip/mec1322')
-rw-r--r-- | chip/mec1322/adc.c | 10 | ||||
-rw-r--r-- | chip/mec1322/clock.c | 4 | ||||
-rw-r--r-- | chip/mec1322/dma.c | 12 | ||||
-rw-r--r-- | chip/mec1322/fan.c | 8 | ||||
-rw-r--r-- | chip/mec1322/gpio.c | 28 | ||||
-rw-r--r-- | chip/mec1322/hwtimer.c | 20 | ||||
-rw-r--r-- | chip/mec1322/i2c.c | 34 | ||||
-rw-r--r-- | chip/mec1322/keyboard_raw.c | 12 | ||||
-rw-r--r-- | chip/mec1322/lfw/ec_lfw.c | 24 | ||||
-rw-r--r-- | chip/mec1322/lpc.c | 38 | ||||
-rw-r--r-- | chip/mec1322/port80.c | 14 | ||||
-rw-r--r-- | chip/mec1322/pwm.c | 4 | ||||
-rw-r--r-- | chip/mec1322/registers.h | 28 | ||||
-rw-r--r-- | chip/mec1322/spi.c | 6 | ||||
-rw-r--r-- | chip/mec1322/system.c | 6 | ||||
-rw-r--r-- | chip/mec1322/uart.c | 38 | ||||
-rw-r--r-- | chip/mec1322/watchdog.c | 18 |
17 files changed, 152 insertions, 152 deletions
diff --git a/chip/mec1322/adc.c b/chip/mec1322/adc.c index a1210fa274..9026cf8a2e 100644 --- a/chip/mec1322/adc.c +++ b/chip/mec1322/adc.c @@ -30,7 +30,7 @@ static int start_single_and_wait(int timeout) task_waiting = task_get_current(); /* Start conversion */ - MEC1322_ADC_CTRL |= 1 << 1; + MEC1322_ADC_CTRL |= BIT(1); /* Wait for interrupt */ event = task_wait_event(timeout); @@ -60,12 +60,12 @@ int adc_read_channel(enum adc_channel ch) static void adc_init(void) { /* Activate ADC module */ - MEC1322_ADC_CTRL |= 1 << 0; + MEC1322_ADC_CTRL |= BIT(0); /* Enable interrupt */ task_waiting = TASK_ID_INVALID; - MEC1322_INT_ENABLE(17) |= 1 << 10; - MEC1322_INT_BLK_EN |= 1 << 17; + MEC1322_INT_ENABLE(17) |= BIT(10); + MEC1322_INT_BLK_EN |= BIT(17); task_enable_irq(MEC1322_IRQ_ADC_SNGL); } DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); @@ -73,7 +73,7 @@ DECLARE_HOOK(HOOK_INIT, adc_init, HOOK_PRIO_INIT_ADC); void adc_interrupt(void) { /* Clear interrupt status bit */ - MEC1322_ADC_CTRL |= 1 << 7; + MEC1322_ADC_CTRL |= BIT(7); if (task_waiting != TASK_ID_INVALID) task_wake(task_waiting); diff --git a/chip/mec1322/clock.c b/chip/mec1322/clock.c index d86f1bc5a7..3f58ef086c 100644 --- a/chip/mec1322/clock.c +++ b/chip/mec1322/clock.c @@ -103,8 +103,8 @@ DECLARE_HOOK(HOOK_INIT, clock_turbo_disable, HOOK_PRIO_INIT_VBOOT_HASH + 1); */ static void htimer_init(void) { - MEC1322_INT_BLK_EN |= 1 << 17; - MEC1322_INT_ENABLE(17) |= 1 << 20; /* GIRQ=17, aggregator bit = 20 */ + MEC1322_INT_BLK_EN |= BIT(17); + MEC1322_INT_ENABLE(17) |= BIT(20); /* GIRQ=17, aggregator bit = 20 */ MEC1322_HTIMER_PRELOAD = 0; /* disable at beginning */ task_enable_irq(MEC1322_IRQ_HTIMER); diff --git a/chip/mec1322/dma.c b/chip/mec1322/dma.c index b354fea2a4..34617c92bc 100644 --- a/chip/mec1322/dma.c +++ b/chip/mec1322/dma.c @@ -27,8 +27,8 @@ void dma_disable(enum dma_channel channel) { mec1322_dma_chan_t *chan = dma_get_channel(channel); - if (chan->ctrl & (1 << 0)) - chan->ctrl &= ~(1 << 0); + if (chan->ctrl & BIT(0)) + chan->ctrl &= ~BIT(0); if (chan->act == 1) chan->act = 0; @@ -42,9 +42,9 @@ void dma_disable_all(void) for (ch = 0; ch < MEC1322_DMAC_COUNT; ch++) { mec1322_dma_chan_t *chan = dma_get_channel(ch); /* Abort any current transfer. */ - chan->ctrl |= (1 << 25); + chan->ctrl |= BIT(25); /* Disable the channel. */ - chan->ctrl &= ~(1 << 0); + chan->ctrl &= ~BIT(0); chan->act = 0; } @@ -69,8 +69,8 @@ static void prepare_channel(mec1322_dma_chan_t *chan, unsigned count, { int xfer_size = (flags >> 20) & 0x7; - if (chan->ctrl & (1 << 0)) - chan->ctrl &= ~(1 << 0); + if (chan->ctrl & BIT(0)) + chan->ctrl &= ~BIT(0); chan->act |= 0x1; chan->dev = (uint32_t)periph; diff --git a/chip/mec1322/fan.c b/chip/mec1322/fan.c index 9636bc816e..0f40ba22be 100644 --- a/chip/mec1322/fan.c +++ b/chip/mec1322/fan.c @@ -81,15 +81,15 @@ int fan_get_duty(int ch) int fan_get_rpm_mode(int ch) { - return !!(MEC1322_FAN_CFG1 & (1 << 7)); + return !!(MEC1322_FAN_CFG1 & BIT(7)); } void fan_set_rpm_mode(int ch, int rpm_mode) { if (rpm_mode) - MEC1322_FAN_CFG1 |= 1 << 7; + MEC1322_FAN_CFG1 |= BIT(7); else - MEC1322_FAN_CFG1 &= ~(1 << 7); + MEC1322_FAN_CFG1 &= ~BIT(7); clear_status(); } @@ -117,7 +117,7 @@ enum fan_status fan_get_status(int ch) { uint8_t sts = MEC1322_FAN_STATUS; - if (sts & ((1 << 5) | (1 << 1))) + if (sts & (BIT(5) | BIT(1))) return FAN_STATUS_FRUSTRATED; if (fan_get_rpm_actual(ch) == 0) return FAN_STATUS_STOPPED; diff --git a/chip/mec1322/gpio.c b/chip/mec1322/gpio.c index 4df46dd6d8..c3b62ad583 100644 --- a/chip/mec1322/gpio.c +++ b/chip/mec1322/gpio.c @@ -37,7 +37,7 @@ void gpio_set_alternate_function(uint32_t port, uint32_t mask, int func) while (mask) { i = __builtin_ffs(mask) - 1; val = MEC1322_GPIO_CTL(port, i); - val &= ~((1 << 12) | (1 << 13)); + val &= ~(BIT(12) | BIT(13)); /* mux_control = 0 indicates GPIO */ if (func > 0) val |= (func & 0x3) << 12; @@ -57,7 +57,7 @@ test_mockable int gpio_get_level(enum gpio_signal signal) i = GPIO_MASK_TO_NUM(mask); val = MEC1322_GPIO_CTL(gpio_list[signal].port, i); - return (val & (1 << 24)) ? 1 : 0; + return (val & BIT(24)) ? 1 : 0; } void gpio_set_level(enum gpio_signal signal, int value) @@ -70,9 +70,9 @@ void gpio_set_level(enum gpio_signal signal, int value) i = GPIO_MASK_TO_NUM(mask); if (value) - MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= (1 << 16); + MEC1322_GPIO_CTL(gpio_list[signal].port, i) |= BIT(16); else - MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~(1 << 16); + MEC1322_GPIO_CTL(gpio_list[signal].port, i) &= ~BIT(16); } void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) @@ -89,16 +89,16 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) * when changing the line to an output. */ if (flags & GPIO_OPEN_DRAIN) - val |= (1 << 8); + val |= BIT(8); else - val &= ~(1 << 8); + val &= ~BIT(8); if (flags & GPIO_OUTPUT) { - val |= (1 << 9); - val &= ~(1 << 10); + val |= BIT(9); + val &= ~BIT(10); } else { - val &= ~(1 << 9); - val |= (1 << 10); + val &= ~BIT(9); + val |= BIT(10); } /* Handle pullup / pulldown */ @@ -111,9 +111,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* Set up interrupt */ if (flags & (GPIO_INT_F_RISING | GPIO_INT_F_FALLING)) - val |= (1 << 7); + val |= BIT(7); else - val &= ~(1 << 7); + val &= ~BIT(7); val &= ~(0x7 << 4); @@ -130,9 +130,9 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags) /* Set up level */ if (flags & GPIO_HIGH) - val |= (1 << 16); + val |= BIT(16); else if (flags & GPIO_LOW) - val &= ~(1 << 16); + val &= ~BIT(16); MEC1322_GPIO_CTL(port, i) = val; } diff --git a/chip/mec1322/hwtimer.c b/chip/mec1322/hwtimer.c index be9ffac1ea..4adaa38516 100644 --- a/chip/mec1322/hwtimer.c +++ b/chip/mec1322/hwtimer.c @@ -17,7 +17,7 @@ void __hw_clock_event_set(uint32_t deadline) { MEC1322_TMR32_CNT(1) = MEC1322_TMR32_CNT(0) - (0xffffffff - deadline); - MEC1322_TMR32_CTL(1) |= (1 << 5); + MEC1322_TMR32_CTL(1) |= BIT(5); } uint32_t __hw_clock_event_get(void) @@ -27,7 +27,7 @@ uint32_t __hw_clock_event_get(void) void __hw_clock_event_clear(void) { - MEC1322_TMR32_CTL(1) &= ~(1 << 5); + MEC1322_TMR32_CTL(1) &= ~BIT(5); } uint32_t __hw_clock_source_read(void) @@ -37,9 +37,9 @@ uint32_t __hw_clock_source_read(void) void __hw_clock_source_set(uint32_t ts) { - MEC1322_TMR32_CTL(0) &= ~(1 << 5); + MEC1322_TMR32_CTL(0) &= ~BIT(5); MEC1322_TMR32_CNT(0) = 0xffffffff - ts; - MEC1322_TMR32_CTL(0) |= (1 << 5); + MEC1322_TMR32_CTL(0) |= BIT(5); } static void __hw_clock_source_irq(int timer_id) @@ -60,10 +60,10 @@ static void configure_timer(int timer_id) uint32_t val; /* Ensure timer is not running */ - MEC1322_TMR32_CTL(timer_id) &= ~(1 << 5); + MEC1322_TMR32_CTL(timer_id) &= ~BIT(5); /* Enable timer */ - MEC1322_TMR32_CTL(timer_id) |= (1 << 0); + MEC1322_TMR32_CTL(timer_id) |= BIT(0); val = MEC1322_TMR32_CTL(timer_id); @@ -94,16 +94,16 @@ int __hw_clock_source_init(uint32_t start_t) MEC1322_TMR32_CNT(0) = 0xffffffff - start_t; /* Auto restart */ - MEC1322_TMR32_CTL(0) |= (1 << 3); + MEC1322_TMR32_CTL(0) |= BIT(3); /* Start counting in timer 0 */ - MEC1322_TMR32_CTL(0) |= (1 << 5); + MEC1322_TMR32_CTL(0) |= BIT(5); /* Enable interrupt */ task_enable_irq(MEC1322_IRQ_TIMER32_0); task_enable_irq(MEC1322_IRQ_TIMER32_1); - MEC1322_INT_ENABLE(23) |= (1 << 4) | (1 << 5); - MEC1322_INT_BLK_EN |= (1 << 23); + MEC1322_INT_ENABLE(23) |= BIT(4) | BIT(5); + MEC1322_INT_BLK_EN |= BIT(23); return MEC1322_IRQ_TIMER32_1; } diff --git a/chip/mec1322/i2c.c b/chip/mec1322/i2c.c index ce3e618c24..2c22256d81 100644 --- a/chip/mec1322/i2c.c +++ b/chip/mec1322/i2c.c @@ -21,22 +21,22 @@ #define I2C_CLOCK 16000000 /* 16 MHz */ /* Status */ -#define STS_NBB (1 << 0) /* Bus busy */ -#define STS_LAB (1 << 1) /* Arbitration lost */ -#define STS_LRB (1 << 3) /* Last received bit */ -#define STS_BER (1 << 4) /* Bus error */ -#define STS_PIN (1 << 7) /* Pending interrupt */ +#define STS_NBB BIT(0) /* Bus busy */ +#define STS_LAB BIT(1) /* Arbitration lost */ +#define STS_LRB BIT(3) /* Last received bit */ +#define STS_BER BIT(4) /* Bus error */ +#define STS_PIN BIT(7) /* Pending interrupt */ /* Control */ -#define CTRL_ACK (1 << 0) /* Acknowledge */ -#define CTRL_STO (1 << 1) /* STOP */ -#define CTRL_STA (1 << 2) /* START */ -#define CTRL_ENI (1 << 3) /* Enable interrupt */ -#define CTRL_ESO (1 << 6) /* Enable serial output */ -#define CTRL_PIN (1 << 7) /* Pending interrupt not */ +#define CTRL_ACK BIT(0) /* Acknowledge */ +#define CTRL_STO BIT(1) /* STOP */ +#define CTRL_STA BIT(2) /* START */ +#define CTRL_ENI BIT(3) /* Enable interrupt */ +#define CTRL_ESO BIT(6) /* Enable serial output */ +#define CTRL_PIN BIT(7) /* Pending interrupt not */ /* Completion */ -#define COMP_IDLE (1 << 29) /* i2c bus is idle */ +#define COMP_IDLE BIT(29) /* i2c bus is idle */ #define COMP_RW_BITS_MASK 0x3C /* R/W bits mask */ /* Maximum transfer of a SMBUS block transfer */ @@ -116,21 +116,21 @@ static void configure_controller(int controller, int kbps) configure_controller_speed(controller, kbps); MEC1322_I2C_CTRL(controller) = CTRL_PIN | CTRL_ESO | CTRL_ACK | CTRL_ENI; - MEC1322_I2C_CONFIG(controller) |= 1 << 10; /* ENAB */ + MEC1322_I2C_CONFIG(controller) |= BIT(10); /* ENAB */ /* Enable interrupt */ - MEC1322_I2C_CONFIG(controller) |= 1 << 29; /* ENIDI */ + MEC1322_I2C_CONFIG(controller) |= BIT(29); /* ENIDI */ MEC1322_INT_ENABLE(12) |= (1 << controller); - MEC1322_INT_BLK_EN |= 1 << 12; + MEC1322_INT_BLK_EN |= BIT(12); } static void reset_controller(int controller) { int i; - MEC1322_I2C_CONFIG(controller) |= 1 << 9; + MEC1322_I2C_CONFIG(controller) |= BIT(9); udelay(100); - MEC1322_I2C_CONFIG(controller) &= ~(1 << 9); + MEC1322_I2C_CONFIG(controller) &= ~BIT(9); for (i = 0; i < i2c_ports_used; ++i) if (controller == i2c_port_to_controller(i2c_ports[i].port)) { diff --git a/chip/mec1322/keyboard_raw.c b/chip/mec1322/keyboard_raw.c index 3269af2cf9..a8a1e6b124 100644 --- a/chip/mec1322/keyboard_raw.c +++ b/chip/mec1322/keyboard_raw.c @@ -19,8 +19,8 @@ void keyboard_raw_init(void) gpio_config_module(MODULE_KEYBOARD_SCAN, 1); /* Enable keyboard scan interrupt */ - MEC1322_INT_ENABLE(17) |= 1 << 21; - MEC1322_INT_BLK_EN |= 1 << 17; + MEC1322_INT_ENABLE(17) |= BIT(21); + MEC1322_INT_BLK_EN |= BIT(17); MEC1322_KS_KSI_INT_EN = 0xff; } @@ -32,19 +32,19 @@ void keyboard_raw_task_start(void) test_mockable void keyboard_raw_drive_column(int out) { if (out == KEYBOARD_COLUMN_ALL) { - MEC1322_KS_KSO_SEL = 1 << 5; /* KSEN=0, KSALL=1 */ + MEC1322_KS_KSO_SEL = BIT(5); /* KSEN=0, KSALL=1 */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 1); #endif } else if (out == KEYBOARD_COLUMN_NONE) { - MEC1322_KS_KSO_SEL = 1 << 6; /* KSEN=1 */ + MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */ #ifdef CONFIG_KEYBOARD_COL2_INVERTED gpio_set_level(GPIO_KBD_KSO2, 0); #endif } else { #ifdef CONFIG_KEYBOARD_COL2_INVERTED if (out == 2) { - MEC1322_KS_KSO_SEL = 1 << 6; /* KSEN=1 */ + MEC1322_KS_KSO_SEL = BIT(6); /* KSEN=1 */ gpio_set_level(GPIO_KBD_KSO2, 1); } else { MEC1322_KS_KSO_SEL = out + CONFIG_KEYBOARD_KSO_BASE; @@ -84,5 +84,5 @@ DECLARE_IRQ(MEC1322_IRQ_KSC_INT, keyboard_raw_interrupt, 1); int keyboard_raw_is_input_low(int port, int id) { - return (MEC1322_GPIO_CTL(port, id) & (1 << 24)) == 0; + return (MEC1322_GPIO_CTL(port, id) & BIT(24)) == 0; } diff --git a/chip/mec1322/lfw/ec_lfw.c b/chip/mec1322/lfw/ec_lfw.c index 86a4949e17..7dacfc3077 100644 --- a/chip/mec1322/lfw/ec_lfw.c +++ b/chip/mec1322/lfw/ec_lfw.c @@ -48,10 +48,10 @@ void timer_init() uint32_t val = 0; /* Ensure timer is not running */ - MEC1322_TMR32_CTL(0) &= ~(1 << 5); + MEC1322_TMR32_CTL(0) &= ~BIT(5); /* Enable timer */ - MEC1322_TMR32_CTL(0) |= (1 << 0); + MEC1322_TMR32_CTL(0) |= BIT(0); val = MEC1322_TMR32_CTL(0); @@ -67,10 +67,10 @@ void timer_init() MEC1322_TMR32_CNT(0) = 0xffffffff; /* Auto restart */ - MEC1322_TMR32_CTL(0) |= (1 << 3); + MEC1322_TMR32_CTL(0) |= BIT(3); /* Start counting in timer 0 */ - MEC1322_TMR32_CTL(0) |= (1 << 5); + MEC1322_TMR32_CTL(0) |= BIT(5); } @@ -146,7 +146,7 @@ void uart_write_c(char c) uart_write_c('\r'); /* Wait for space in transmit FIFO. */ - while (!(MEC1322_UART_LSR & (1 << 5))) + while (!(MEC1322_UART_LSR & BIT(5))) ; MEC1322_UART_TB = c; } @@ -181,31 +181,31 @@ void jump_to_image(uintptr_t init_addr) void uart_init(void) { /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MEC1322_UART_CFG &= ~(1 << 1); + MEC1322_UART_CFG &= ~BIT(1); /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ /* Set CLK_SRC = 0 */ - MEC1322_UART_CFG &= ~(1 << 0); + MEC1322_UART_CFG &= ~BIT(0); /* Set DLAB = 1 */ - MEC1322_UART_LCR |= (1 << 7); + MEC1322_UART_LCR |= BIT(7); /* PBRG0/PBRG1 */ MEC1322_UART_PBRG0 = 1; MEC1322_UART_PBRG1 = 0; /* Set DLAB = 0 */ - MEC1322_UART_LCR &= ~(1 << 7); + MEC1322_UART_LCR &= ~BIT(7); /* Set word length to 8-bit */ - MEC1322_UART_LCR |= (1 << 0) | (1 << 1); + MEC1322_UART_LCR |= BIT(0) | BIT(1); /* Enable FIFO */ - MEC1322_UART_FCR = (1 << 0); + MEC1322_UART_FCR = BIT(0); /* Activate UART */ - MEC1322_UART_ACT |= (1 << 0); + MEC1322_UART_ACT |= BIT(0); gpio_config_module(MODULE_UART, 1); } diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c index 5d2d57f834..829f91a85c 100644 --- a/chip/mec1322/lpc.c +++ b/chip/mec1322/lpc.c @@ -190,23 +190,23 @@ static void setup_lpc(void) gpio_config_module(MODULE_LPC, 1); /* Set up interrupt on LRESET# deassert */ - MEC1322_INT_SOURCE(19) = 1 << 1; - MEC1322_INT_ENABLE(19) |= 1 << 1; - MEC1322_INT_BLK_EN |= 1 << 19; + MEC1322_INT_SOURCE(19) = BIT(1); + MEC1322_INT_ENABLE(19) |= BIT(1); + MEC1322_INT_BLK_EN |= BIT(19); task_enable_irq(MEC1322_IRQ_GIRQ19); /* Set up ACPI0 for 0x62/0x66 */ MEC1322_LPC_ACPI_EC0_BAR = 0x00628304; - MEC1322_INT_ENABLE(15) |= 1 << 6; - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= BIT(6); + MEC1322_INT_BLK_EN |= BIT(15); /* Clear STATUS_PROCESSING bit in case it was set during sysjump */ MEC1322_ACPI_EC_STATUS(0) &= ~EC_LPC_STATUS_PROCESSING; task_enable_irq(MEC1322_IRQ_ACPIEC0_IBF); /* Set up ACPI1 for 0x200/0x204 */ MEC1322_LPC_ACPI_EC1_BAR = 0x02008407; - MEC1322_INT_ENABLE(15) |= 1 << 8; - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= BIT(8); + MEC1322_INT_BLK_EN |= BIT(15); MEC1322_ACPI_EC_STATUS(1) &= ~EC_LPC_STATUS_PROCESSING; task_enable_irq(MEC1322_IRQ_ACPIEC1_IBF); @@ -214,24 +214,24 @@ static void setup_lpc(void) MEC1322_LPC_8042_BAR = 0x00608104; /* Set up indication of Auxiliary sts */ - MEC1322_8042_KB_CTRL |= 1 << 7; + MEC1322_8042_KB_CTRL |= BIT(7); MEC1322_8042_ACT |= 1; - MEC1322_INT_ENABLE(15) |= ((1 << 13) | (1 << 14)); - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= (BIT(13) | BIT(14)); + MEC1322_INT_BLK_EN |= BIT(15); task_enable_irq(MEC1322_IRQ_8042EM_IBF); task_enable_irq(MEC1322_IRQ_8042EM_OBF); #ifndef CONFIG_KEYBOARD_IRQ_GPIO /* Set up SERIRQ for keyboard */ - MEC1322_8042_KB_CTRL |= (1 << 5); + MEC1322_8042_KB_CTRL |= BIT(5); MEC1322_LPC_SIRQ(1) = 0x01; #endif /* Set up EMI module for memory mapped region, base address 0x800 */ MEC1322_LPC_EMI_BAR = 0x0800800f; - MEC1322_INT_ENABLE(15) |= 1 << 2; - MEC1322_INT_BLK_EN |= 1 << 15; + MEC1322_INT_ENABLE(15) |= BIT(2); + MEC1322_INT_BLK_EN |= BIT(15); task_enable_irq(MEC1322_IRQ_EMI); /* Access data RAM through alias address */ @@ -295,7 +295,7 @@ DECLARE_DEFERRED(lpc_chipset_reset); void girq19_interrupt(void) { /* Check interrupt result for LRESET# trigger */ - if (MEC1322_INT_RESULT(19) & (1 << 1)) { + if (MEC1322_INT_RESULT(19) & BIT(1)) { /* Initialize LPC module when LRESET# is deasserted */ if (!lpc_get_pltrst_asserted()) { setup_lpc(); @@ -313,7 +313,7 @@ void girq19_interrupt(void) lpc_get_pltrst_asserted() ? "" : "de"); /* Clear interrupt source */ - MEC1322_INT_SOURCE(19) = 1 << 1; + MEC1322_INT_SOURCE(19) = BIT(1); } } DECLARE_IRQ(MEC1322_IRQ_GIRQ19, girq19_interrupt, 1); @@ -423,7 +423,7 @@ void kb_ibf_interrupt(void) { if (lpc_keyboard_input_pending()) keyboard_host_write(MEC1322_8042_H2E, - MEC1322_8042_STS & (1 << 3)); + MEC1322_8042_STS & BIT(3)); task_wake(TASK_ID_KEYPROTO); } DECLARE_IRQ(MEC1322_IRQ_8042EM_IBF, kb_ibf_interrupt, 1); @@ -437,12 +437,12 @@ DECLARE_IRQ(MEC1322_IRQ_8042EM_OBF, kb_obf_interrupt, 1); int lpc_keyboard_has_char(void) { - return (MEC1322_8042_STS & (1 << 0)) ? 1 : 0; + return (MEC1322_8042_STS & BIT(0)) ? 1 : 0; } int lpc_keyboard_input_pending(void) { - return (MEC1322_8042_STS & (1 << 1)) ? 1 : 0; + return (MEC1322_8042_STS & BIT(1)) ? 1 : 0; } void lpc_keyboard_put_char(uint8_t chr, int send_irq) @@ -506,7 +506,7 @@ static int lpc_get_protocol_info(struct host_cmd_handler_args *args) struct ec_response_get_protocol_info *r = args->response; memset(r, 0, sizeof(*r)); - r->protocol_versions = (1 << 3); + r->protocol_versions = BIT(3); r->max_request_packet_size = EC_LPC_HOST_PACKET_SIZE; r->max_response_packet_size = EC_LPC_HOST_PACKET_SIZE; r->flags = 0; diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c index fa4fd36a4f..df4583ed8b 100644 --- a/chip/mec1322/port80.c +++ b/chip/mec1322/port80.c @@ -31,7 +31,7 @@ static void port_80_interrupt_enable(void) /* Enable the interrupt. */ task_enable_irq(MEC1322_IRQ_TIMER16_1); /* Enable and start the timer. */ - MEC1322_TMR16_CTL(1) |= 1 | (1 << 5); + MEC1322_TMR16_CTL(1) |= 1 | BIT(5); } DECLARE_HOOK(HOOK_CHIPSET_RESUME, port_80_interrupt_enable, HOOK_PRIO_DEFAULT); DECLARE_HOOK(HOOK_CHIPSET_RESET, port_80_interrupt_enable, HOOK_PRIO_DEFAULT); @@ -61,9 +61,9 @@ static void port_80_interrupt_init(void) val = MEC1322_TMR16_CTL(1); val = (val & 0xFFFF) | (47 << 16); /* Automatically restart the timer. */ - val |= (1 << 3); + val |= BIT(3); /* The counter should decrement. */ - val &= ~(1 << 2); + val &= ~BIT(2); MEC1322_TMR16_CTL(1) = val; /* Set the reload value(us). */ @@ -73,12 +73,12 @@ static void port_80_interrupt_init(void) MEC1322_TMR16_STS(1) |= 1; /* Clear any pending interrupt. */ - MEC1322_INT_SOURCE(23) = (1 << 1); + MEC1322_INT_SOURCE(23) = BIT(1); /* Enable IRQ vector 23. */ - MEC1322_INT_BLK_EN |= (1 << 23); + MEC1322_INT_BLK_EN |= BIT(23); /* Enable the interrupt. */ MEC1322_TMR16_IEN(1) |= 1; - MEC1322_INT_ENABLE(23) = (1 << 1); + MEC1322_INT_ENABLE(23) = BIT(1); port_80_interrupt_enable(); } @@ -89,7 +89,7 @@ void port_80_interrupt(void) int data; MEC1322_TMR16_STS(1) = 1; /* Ack the interrupt */ - if ((1 << 1) & MEC1322_INT_RESULT(23)) { + if (BIT(1) & MEC1322_INT_RESULT(23)) { data = port_80_read(); if (data != PORT_80_IGNORE) { diff --git a/chip/mec1322/pwm.c b/chip/mec1322/pwm.c index 64547490f4..314f92fb6a 100644 --- a/chip/mec1322/pwm.c +++ b/chip/mec1322/pwm.c @@ -67,8 +67,8 @@ static void pwm_configure(int ch, int active_low, int clock_low) * clock_low=1 selects the 100kHz_Clk source */ MEC1322_PWM_CFG(ch) = (15 << 3) | /* Pre-divider = 16 */ - (active_low ? (1 << 2) : 0) | - (clock_low ? (1 << 1) : 0); + (active_low ? BIT(2) : 0) | + (clock_low ? BIT(1) : 0); } static void pwm_init(void) diff --git a/chip/mec1322/registers.h b/chip/mec1322/registers.h index c36e72b089..877a48ff7a 100644 --- a/chip/mec1322/registers.h +++ b/chip/mec1322/registers.h @@ -28,10 +28,10 @@ /* Command all blocks to sleep */ #define MEC1322_PCR_EC_SLP_EN_SLEEP 0xe0700ff7 #define MEC1322_PCR_EC_SLP_EN_PWM(n) (1 << ((n) ? (19 + (n)) : 4)) -#define MEC1322_PCR_EC_SLP_EN_PWM3 (1 << 22) -#define MEC1322_PCR_EC_SLP_EN_PWM2 (1 << 21) -#define MEC1322_PCR_EC_SLP_EN_PWM1 (1 << 20) -#define MEC1322_PCR_EC_SLP_EN_PWM0 (1 << 4) +#define MEC1322_PCR_EC_SLP_EN_PWM3 BIT(22) +#define MEC1322_PCR_EC_SLP_EN_PWM2 BIT(21) +#define MEC1322_PCR_EC_SLP_EN_PWM1 BIT(20) +#define MEC1322_PCR_EC_SLP_EN_PWM0 BIT(4) /* Allow all blocks to request clocks */ #define MEC1322_PCR_EC_SLP_EN_WAKE (~0xe0700ff7) #define MEC1322_PCR_EC_CLK_REQ REG32(MEC1322_PCR_BASE + 0xc) @@ -59,8 +59,8 @@ #define MEC1322_PCR_PWR_RST_CTL REG32(MEC1322_PCR_BASE + 0x48) /* Bit defines for MEC1322_PCR_CHIP_PWR_RST */ -#define MEC1322_PWR_RST_STS_VCC1 (1 << 6) -#define MEC1322_PWR_RST_STS_VBAT (1 << 5) +#define MEC1322_PWR_RST_STS_VCC1 BIT(6) +#define MEC1322_PWR_RST_STS_VBAT BIT(5) /* EC Subsystem */ #define MEC1322_EC_BASE 0x4000fc00 @@ -106,7 +106,7 @@ #define MEC1322_UART_SCR REG8(MEC1322_UART_RUNTIME_BASE + 0x7) /* Bit defines for MEC1322_UART_LSR */ -#define MEC1322_LSR_TX_EMPTY (1 << 5) +#define MEC1322_LSR_TX_EMPTY BIT(5) /* GPIO */ #define MEC1322_GPIO_BASE 0x40081000 @@ -152,7 +152,7 @@ static inline uintptr_t gpio_port_base(int port_id) #define MEC1322_VBAT_RAM(x) REG32(MEC1322_VBAT_BASE + 0x400 + 4 * (x)) /* Bit definition for MEC1322_VBAT_STS */ -#define MEC1322_VBAT_STS_WDT (1 << 5) +#define MEC1322_VBAT_STS_WDT BIT(5) /* Miscellaneous firmware control fields * scratch pad index cannot be more than 16 as @@ -416,14 +416,14 @@ typedef volatile struct mec1322_dma_regs mec1322_dma_regs_t; #define MEC1322_DMA_REGS ((mec1322_dma_regs_t *)MEC1322_DMA_BASE) /* Bits for DMA channel regs */ -#define MEC1322_DMA_ACT_EN (1 << 0) +#define MEC1322_DMA_ACT_EN BIT(0) #define MEC1322_DMA_XFER_SIZE(x) ((x) << 20) -#define MEC1322_DMA_INC_DEV (1 << 17) -#define MEC1322_DMA_INC_MEM (1 << 16) +#define MEC1322_DMA_INC_DEV BIT(17) +#define MEC1322_DMA_INC_MEM BIT(16) #define MEC1322_DMA_DEV(x) ((x) << 9) -#define MEC1322_DMA_TO_DEV (1 << 8) -#define MEC1322_DMA_DONE (1 << 2) -#define MEC1322_DMA_RUN (1 << 0) +#define MEC1322_DMA_TO_DEV BIT(8) +#define MEC1322_DMA_DONE BIT(2) +#define MEC1322_DMA_RUN BIT(0) /* IRQ Numbers */ diff --git a/chip/mec1322/spi.c b/chip/mec1322/spi.c index 705a95c44e..f7211f7289 100644 --- a/chip/mec1322/spi.c +++ b/chip/mec1322/spi.c @@ -83,14 +83,14 @@ int spi_transaction_async(const struct spi_device_t *spi_device, gpio_set_level(spi_device->gpio_cs, 0); /* Disable auto read */ - MEC1322_SPI_CR(port) &= ~(1 << 5); + MEC1322_SPI_CR(port) &= ~BIT(5); ret = spi_tx(port, txdata, txlen); if (ret != EC_SUCCESS) return ret; /* Enable auto read */ - MEC1322_SPI_CR(port) |= 1 << 5; + MEC1322_SPI_CR(port) |= BIT(5); if (rxlen != 0) { dma_start_rx(&spi_rx_option[port], rxlen, rxdata); @@ -108,7 +108,7 @@ int spi_transaction_flush(const struct spi_device_t *spi_device) timestamp_t deadline; /* Disable auto read */ - MEC1322_SPI_CR(port) &= ~(1 << 5); + MEC1322_SPI_CR(port) &= ~BIT(5); deadline.val = get_time().val + SPI_BYTE_TRANSFER_TIMEOUT_US; /* Wait for FIFO empty SPISR_TXBE */ diff --git a/chip/mec1322/system.c b/chip/mec1322/system.c index 449d234343..4431ee6954 100644 --- a/chip/mec1322/system.c +++ b/chip/mec1322/system.c @@ -88,7 +88,7 @@ void system_pre_init(void) MEC1322_EC_TRACE_EN &= ~1; /* Deassert nSIO_RESET */ - MEC1322_PCR_PWR_RST_CTL &= ~(1 << 0); + MEC1322_PCR_PWR_RST_CTL &= ~BIT(0); spi_enable(CONFIG_SPI_FLASH_PORT, 1); } @@ -323,8 +323,8 @@ void system_hibernate(uint32_t seconds, uint32_t microseconds) } if (seconds || microseconds) { - MEC1322_INT_BLK_EN |= 1 << 17; - MEC1322_INT_ENABLE(17) |= 1 << 20; + MEC1322_INT_BLK_EN |= BIT(17); + MEC1322_INT_ENABLE(17) |= BIT(20); interrupt_enable(); task_enable_irq(MEC1322_IRQ_HTIMER); if (seconds > 2) { diff --git a/chip/mec1322/uart.c b/chip/mec1322/uart.c index ddbe113c7d..af4ccc5b46 100644 --- a/chip/mec1322/uart.c +++ b/chip/mec1322/uart.c @@ -29,7 +29,7 @@ int uart_init_done(void) void uart_tx_start(void) { /* If interrupt is already enabled, nothing to do */ - if (MEC1322_UART_IER & (1 << 1)) + if (MEC1322_UART_IER & BIT(1)) return; /* Do not allow deep sleep while transmit in progress */ @@ -41,13 +41,13 @@ void uart_tx_start(void) * UART where the FIFO only triggers the interrupt when its * threshold is _crossed_, not just met. */ - MEC1322_UART_IER |= (1 << 1); + MEC1322_UART_IER |= BIT(1); task_trigger_irq(MEC1322_IRQ_UART); } void uart_tx_stop(void) { - MEC1322_UART_IER &= ~(1 << 1); + MEC1322_UART_IER &= ~BIT(1); /* Re-allow deep sleep */ enable_sleep(SLEEP_MASK_UART); @@ -77,7 +77,7 @@ int uart_tx_in_progress(void) int uart_rx_available(void) { - return MEC1322_UART_LSR & (1 << 0); + return MEC1322_UART_LSR & BIT(0); } void uart_write_char(char c) @@ -97,7 +97,7 @@ int uart_read_char(void) static void uart_clear_rx_fifo(int channel) { - MEC1322_UART_FCR = (1 << 0) | (1 << 1); + MEC1322_UART_FCR = BIT(0) | BIT(1); } /** @@ -114,31 +114,31 @@ DECLARE_IRQ(MEC1322_IRQ_UART, uart_ec_interrupt, 1); void uart_init(void) { /* Set UART to reset on VCC1_RESET instaed of nSIO_RESET */ - MEC1322_UART_CFG &= ~(1 << 1); + MEC1322_UART_CFG &= ~BIT(1); /* Baud rate = 115200. 1.8432MHz clock. Divisor = 1 */ /* Set CLK_SRC = 0 */ - MEC1322_UART_CFG &= ~(1 << 0); + MEC1322_UART_CFG &= ~BIT(0); /* Set DLAB = 1 */ - MEC1322_UART_LCR |= (1 << 7); + MEC1322_UART_LCR |= BIT(7); /* PBRG0/PBRG1 */ MEC1322_UART_PBRG0 = 1; MEC1322_UART_PBRG1 = 0; /* Set DLAB = 0 */ - MEC1322_UART_LCR &= ~(1 << 7); + MEC1322_UART_LCR &= ~BIT(7); /* Set word length to 8-bit */ - MEC1322_UART_LCR |= (1 << 0) | (1 << 1); + MEC1322_UART_LCR |= BIT(0) | BIT(1); /* Enable FIFO */ - MEC1322_UART_FCR = (1 << 0); + MEC1322_UART_FCR = BIT(0); /* Activate UART */ - MEC1322_UART_ACT |= (1 << 0); + MEC1322_UART_ACT |= BIT(0); /* clock_enable_peripheral(CGC_OFFSET_UART, mask, @@ -150,10 +150,10 @@ void uart_init(void) * Enable interrupts for UART0. */ uart_clear_rx_fifo(0); - MEC1322_UART_IER |= (1 << 0); - MEC1322_UART_MCR |= (1 << 3); - MEC1322_INT_ENABLE(15) |= (1 << 0); - MEC1322_INT_BLK_EN |= (1 << 15); + MEC1322_UART_IER |= BIT(0); + MEC1322_UART_MCR |= BIT(3); + MEC1322_INT_ENABLE(15) |= BIT(0); + MEC1322_INT_BLK_EN |= BIT(15); task_enable_irq(MEC1322_IRQ_UART); init_done = 1; @@ -172,7 +172,7 @@ void uart_enter_dsleep(void) gpio_reset(GPIO_UART0_RX); /* power-down/de-activate UART0 */ - MEC1322_UART_ACT &= ~(1 << 0); + MEC1322_UART_ACT &= ~BIT(0); /* Clear pending interrupts on GPIO_UART0_RX(GPIO162, girq=8, bit=18) */ MEC1322_INT_SOURCE(8) = (1<<18); @@ -191,7 +191,7 @@ void uart_exit_dsleep(void) * Note: we can't disable this interrupt if it has already fired * because then the IRQ will not run at all. */ - if (!((1 << 18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */ + if (!(BIT(18) & MEC1322_INT_SOURCE(8))) /* if edge interrupt */ gpio_disable_interrupt(GPIO_UART0_RX); /* Configure UART0 pins for use in UART peripheral. */ @@ -202,7 +202,7 @@ void uart_exit_dsleep(void) task_enable_irq(MEC1322_IRQ_UART); /* NVIC interrupt for UART = 13 */ /* power-up/activate UART0 */ - MEC1322_UART_ACT |= (1 << 0); + MEC1322_UART_ACT |= BIT(0); } void uart_deepsleep_interrupt(enum gpio_signal signal) diff --git a/chip/mec1322/watchdog.c b/chip/mec1322/watchdog.c index a92b57f8a2..07724ca5ee 100644 --- a/chip/mec1322/watchdog.c +++ b/chip/mec1322/watchdog.c @@ -16,9 +16,9 @@ void watchdog_reload(void) #ifdef CONFIG_WATCHDOG_HELP /* Reload the auxiliary timer */ - MEC1322_TMR16_CTL(0) &= ~(1 << 5); + MEC1322_TMR16_CTL(0) &= ~BIT(5); MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MEC1322_TMR16_CTL(0) |= 1 << 5; + MEC1322_TMR16_CTL(0) |= BIT(5); #endif } DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT); @@ -34,10 +34,10 @@ int watchdog_init(void) */ /* Stop the auxiliary timer if it's running */ - MEC1322_TMR16_CTL(0) &= ~(1 << 5); + MEC1322_TMR16_CTL(0) &= ~BIT(5); /* Enable auxiliary timer */ - MEC1322_TMR16_CTL(0) |= 1 << 0; + MEC1322_TMR16_CTL(0) |= BIT(0); val = MEC1322_TMR16_CTL(0); @@ -45,22 +45,22 @@ int watchdog_init(void) val = (val & 0xffff) | (47999 << 16); /* No auto restart */ - val &= ~(1 << 3); + val &= ~BIT(3); /* Count down */ - val &= ~(1 << 2); + val &= ~BIT(2); MEC1322_TMR16_CTL(0) = val; /* Enable interrupt from auxiliary timer */ MEC1322_TMR16_IEN(0) |= 1; task_enable_irq(MEC1322_IRQ_TIMER16_0); - MEC1322_INT_ENABLE(23) |= 1 << 0; - MEC1322_INT_BLK_EN |= 1 << 23; + MEC1322_INT_ENABLE(23) |= BIT(0); + MEC1322_INT_BLK_EN |= BIT(23); /* Load and start the auxiliary timer */ MEC1322_TMR16_CNT(0) = CONFIG_AUX_TIMER_PERIOD_MS; - MEC1322_TMR16_CNT(0) |= 1 << 5; + MEC1322_TMR16_CNT(0) |= BIT(5); #endif /* Set timeout. It takes 1007us to decrement WDG_CNT by 1. */ |