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| author | Rong Chang <rongchang@chromium.org> | 2018-09-05 16:36:12 -0400 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-12-20 13:49:38 -0800 |
| commit | b437f03578e7e19a0ff369fe7ac574ab4414d588 (patch) | |
| tree | d0858fbd1b7b4daa7799cf788dcf24c3d7663c69 /chip/mt_scp/config_chip.h | |
| parent | fd13a286bc99cc2e56e3ef1bb82fcdb63734985a (diff) | |
| download | chrome-ec-b437f03578e7e19a0ff369fe7ac574ab4414d588.tar.gz | |
scp: Add mt_scp chip
SCP is a Cortex-M4 based sensor hub in Mediatek SoC. This change adds
the chip folder and system level drivers.
BRANCH=none
BUG=b:114326670
TEST=manual
make BOARD=kukui_scp -j
copy ec.bin to /lib/firmware/scp.img
echo 'stop' > /sys/class/remoteproc/remoteproc0/state
echo 'start' > /sys/class/remoteproc/remoteproc0/state
check EC uart console
Change-Id: I6629149f352184108fa520e80b59fd2ce94c76f7
Signed-off-by: Rong Chang <rongchang@chromium.org>
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1208770
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/mt_scp/config_chip.h')
| -rw-r--r-- | chip/mt_scp/config_chip.h | 78 |
1 files changed, 78 insertions, 0 deletions
diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h new file mode 100644 index 0000000000..fb303fe815 --- /dev/null +++ b/chip/mt_scp/config_chip.h @@ -0,0 +1,78 @@ +/* Copyright 2018 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_EC_CONFIG_CHIP_H +#define __CROS_EC_CONFIG_CHIP_H + +#include "core/cortex-m/config_core.h" + +/* Interval between HOOK_TICK notifications */ +#define HOOK_TICK_INTERVAL_MS 500 +#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) + +/* Default to UART 2 (AP UART) for EC console */ +#define CONFIG_UART_CONSOLE 2 + +/* Number of IRQ vectors */ +#define CONFIG_IRQ_COUNT 56 + +/* + * Number of EINT can be 0 ~ 160. Change this to conditional macro + * on adding other variants. + */ +#define MAX_NUM_EINT 8 +#define MAX_EINT_PORT (MAX_NUM_EINT / 32) + +/* RW only, no flash + * +-------------------- 0x0 + * | free shared space with AP + * +-------------------- 0x005B0 + * | IPI shared buffer with AP (288 + 8) * 2 + * +-------------------- 0x00800 + * | scp.img, exception vectors starting location. + * +-------------------- 0x7B800 + * | free shared space with AP 2KB + * +-------------------- 0x7C000 + * | 8KB I-CACHE + * +-------------------- 0x7E000 + * | 8KB D-CACHE + * +-------------------- 0x80000 + */ +#undef CONFIG_FW_INCLUDE_RO +#define CONFIG_RAM_BASE 0x00800 +#define CONFIG_RAM_SIZE 0x7B000 +#define CONFIG_RO_MEM_OFF 0 +#define CONFIG_RO_SIZE 0 +#define CONFIG_RW_MEM_OFF 0 +#define CONFIG_RW_SIZE 0x40000 /* 256KB */ +#define CONFIG_EC_WRITABLE_STORAGE_OFF 0 +#define CONFIG_EC_PROTECTED_STORAGE_OFF 0 +#define CONFIG_RO_STORAGE_OFF 0 +#define CONFIG_RW_STORAGE_OFF 0 +#define CONFIG_PROGRAM_MEMORY_BASE 0 +#define CONFIG_MAPPED_STORAGE_BASE 0 + +/* Unsupported features/commands */ +#undef CONFIG_CMD_FLASHINFO +#undef CONFIG_CMD_POWER_AP +#undef CONFIG_FLASH +#undef CONFIG_FLASH_PHYSICAL +#undef CONFIG_FMAP +#undef CONFIG_HIBERNATE + +/* Task stack size */ +#define CONFIG_STACK_SIZE 1024 +#define IDLE_TASK_STACK_SIZE 256 +#define SMALLER_TASK_STACK_SIZE 384 +#define TASK_STACK_SIZE 488 +#define LARGER_TASK_STACK_SIZE 640 +#define VENTI_TASK_STACK_SIZE 768 + +#define CONFIG_CHIP_PRE_INIT + +#define GPIO_PIN(num) ((num) / 32), ((num) % 32) +#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m) + +#endif /* __CROS_EC_CONFIG_CHIP_H */ |