diff options
author | Tom Hughes <tomhughes@chromium.org> | 2022-09-21 14:08:36 -0700 |
---|---|---|
committer | Tom Hughes <tomhughes@chromium.org> | 2022-09-22 12:59:38 -0700 |
commit | c453fd704268ef72de871b0c5ac7a989de662334 (patch) | |
tree | fcf6ce5810f9ff9e3c8cce434812dd75492269ed /chip/mt_scp/mt818x/serial_reg.h | |
parent | 6c1587ca70f558b4f96b3f0b18ad8b027d3ba99d (diff) | |
parent | 28712dae9d7ed1e694f7622cc083afa71090d4d5 (diff) | |
download | chrome-ec-c453fd704268ef72de871b0c5ac7a989de662334.tar.gz |
Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release
Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release
Relevant changes:
git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh
ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header
BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
Test "aes": PASSED
Test "cec": PASSED
Test "cortexm_fpu": PASSED
Test "crc": PASSED
Test "flash_physical": PASSED
Test "flash_write_protect": PASSED
Test "fpsensor_hw": PASSED
Test "fpsensor_spi_ro": PASSED
Test "fpsensor_spi_rw": PASSED
Test "fpsensor_uart_ro": PASSED
Test "fpsensor_uart_rw": PASSED
Test "mpu_ro": PASSED
Test "mpu_rw": PASSED
Test "mutex": PASSED
Test "pingpong": PASSED
Test "printf": PASSED
Test "queue": PASSED
Test "rollback_region0": PASSED
Test "rollback_region1": PASSED
Test "rollback_entropy": PASSED
Test "rtc": PASSED
Test "sha256": PASSED
Test "sha256_unrolled": PASSED
Test "static_if": PASSED
Test "stdlib": PASSED
Test "system_is_locked_wp_on": PASSED
Test "system_is_locked_wp_off": PASSED
Test "timer_dos": PASSED
Test "utils": PASSED
Test "utils_str": PASSED
Test "panic_data_dartmonkey_v2.0.2887": PASSED
Test "panic_data_nocturne_fp_v2.2.64": PASSED
Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7
Diffstat (limited to 'chip/mt_scp/mt818x/serial_reg.h')
-rw-r--r-- | chip/mt_scp/mt818x/serial_reg.h | 110 |
1 files changed, 55 insertions, 55 deletions
diff --git a/chip/mt_scp/mt818x/serial_reg.h b/chip/mt_scp/mt818x/serial_reg.h index 5344566272..8dd2864a98 100644 --- a/chip/mt_scp/mt818x/serial_reg.h +++ b/chip/mt_scp/mt818x/serial_reg.h @@ -1,4 +1,4 @@ -/* Copyright 2018 The Chromium OS Authors. All rights reserved. +/* Copyright 2018 The ChromiumOS Authors * Use of this source code is governed by a BSD-style license that can be * found in the LICENSE file. * @@ -19,72 +19,72 @@ * (Read) Rcvr buffer register * (Write) Xmit holding register */ -#define UART_DATA(n) UART_REG(n, 0) +#define UART_DATA(n) UART_REG(n, 0) /* (Write) Interrupt enable register */ -#define UART_IER(n) UART_REG(n, 1) -#define UART_IER_RDI BIT(0) /* Recv data int */ -#define UART_IER_THRI BIT(1) /* Xmit holding register int */ -#define UART_IER_RLSI BIT(2) /* Rcvr line status int */ -#define UART_IER_MSI BIT(3) /* Modem status int */ +#define UART_IER(n) UART_REG(n, 1) +#define UART_IER_RDI BIT(0) /* Recv data int */ +#define UART_IER_THRI BIT(1) /* Xmit holding register int */ +#define UART_IER_RLSI BIT(2) /* Rcvr line status int */ +#define UART_IER_MSI BIT(3) /* Modem status int */ /* (Read) Interrupt ID register */ -#define UART_IIR(n) UART_REG(n, 2) -#define UART_IIR_NO_INT BIT(0) /* No int pending */ -#define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */ -#define UART_IIR_MSI 0x00 -#define UART_IIR_THRI 0x02 -#define UART_IIR_RDI 0x04 -#define UART_IIR_RLSI 0x06 -#define UART_IIR_BUSY 0x07 /* DW APB busy */ +#define UART_IIR(n) UART_REG(n, 2) +#define UART_IIR_NO_INT BIT(0) /* No int pending */ +#define UART_IIR_ID_MASK 0x0e /* Interrupt ID mask */ +#define UART_IIR_MSI 0x00 +#define UART_IIR_THRI 0x02 +#define UART_IIR_RDI 0x04 +#define UART_IIR_RLSI 0x06 +#define UART_IIR_BUSY 0x07 /* DW APB busy */ /* (Write) FIFO control register */ -#define UART_FCR(n) UART_REG(n, 2) -#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */ -#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */ -#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */ -#define UART_FCR_DMA_SELECT BIT(3) +#define UART_FCR(n) UART_REG(n, 2) +#define UART_FCR_ENABLE_FIFO BIT(0) /* Enable FIFO */ +#define UART_FCR_CLEAR_RCVR BIT(1) /* Clear rcvr FIFO */ +#define UART_FCR_CLEAR_XMIT BIT(2) /* Clear xmit FIFO */ +#define UART_FCR_DMA_SELECT BIT(3) /* FIFO trigger levels */ -#define UART_FCR_T_TRIG_00 0x00 -#define UART_FCR_T_TRIG_01 0x10 -#define UART_FCR_T_TRIG_10 0x20 -#define UART_FCR_T_TRIG_11 0x30 -#define UART_FCR_R_TRIG_00 0x00 -#define UART_FCR_R_TRIG_01 0x40 -#define UART_FCR_R_TRIG_10 0x80 -#define UART_FCR_R_TRIG_11 0x80 +#define UART_FCR_T_TRIG_00 0x00 +#define UART_FCR_T_TRIG_01 0x10 +#define UART_FCR_T_TRIG_10 0x20 +#define UART_FCR_T_TRIG_11 0x30 +#define UART_FCR_R_TRIG_00 0x00 +#define UART_FCR_R_TRIG_01 0x40 +#define UART_FCR_R_TRIG_10 0x80 +#define UART_FCR_R_TRIG_11 0x80 /* (Write) Line control register */ -#define UART_LCR(n) UART_REG(n, 3) -#define UART_LCR_WLEN5 0 /* Word length 5 bits */ -#define UART_LCR_WLEN6 1 -#define UART_LCR_WLEN7 2 -#define UART_LCR_WLEN8 3 -#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */ -#define UART_LCR_PARITY BIT(3) /* Parity enable */ -#define UART_LCR_EPAR BIT(4) /* Even parity */ -#define UART_LCR_SPAR BIT(5) /* Stick parity */ -#define UART_LCR_SBC BIT(6) /* Set break control */ -#define UART_LCR_DLAB BIT(7) /* Divisor latch access */ +#define UART_LCR(n) UART_REG(n, 3) +#define UART_LCR_WLEN5 0 /* Word length 5 bits */ +#define UART_LCR_WLEN6 1 +#define UART_LCR_WLEN7 2 +#define UART_LCR_WLEN8 3 +#define UART_LCR_STOP BIT(2) /* Stop bits: 1bit, 2bits */ +#define UART_LCR_PARITY BIT(3) /* Parity enable */ +#define UART_LCR_EPAR BIT(4) /* Even parity */ +#define UART_LCR_SPAR BIT(5) /* Stick parity */ +#define UART_LCR_SBC BIT(6) /* Set break control */ +#define UART_LCR_DLAB BIT(7) /* Divisor latch access */ /* (Write) Modem control register */ -#define UART_MCR(n) UART_REG(n, 4) +#define UART_MCR(n) UART_REG(n, 4) /* (Read) Line status register */ -#define UART_LSR(n) UART_REG(n, 5) -#define UART_LSR_DR BIT(0) /* Data ready */ -#define UART_LSR_OE BIT(1) /* Overrun error */ -#define UART_LSR_PE BIT(2) /* Parity error */ -#define UART_LSR_FE BIT(3) /* Frame error */ -#define UART_LSR_BI BIT(4) /* Break interrupt */ -#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */ -#define UART_LSR_TEMT BIT(6) /* Xmit empty */ -#define UART_LSR_FIFOE BIT(7) /* FIFO error */ +#define UART_LSR(n) UART_REG(n, 5) +#define UART_LSR_DR BIT(0) /* Data ready */ +#define UART_LSR_OE BIT(1) /* Overrun error */ +#define UART_LSR_PE BIT(2) /* Parity error */ +#define UART_LSR_FE BIT(3) /* Frame error */ +#define UART_LSR_BI BIT(4) /* Break interrupt */ +#define UART_LSR_THRE BIT(5) /* Xmit-hold-register empty */ +#define UART_LSR_TEMT BIT(6) /* Xmit empty */ +#define UART_LSR_FIFOE BIT(7) /* FIFO error */ /* DLAB == 1 */ /* (Write) Divisor latch */ -#define UART_DLL(n) UART_REG(n, 0) /* Low */ -#define UART_DLH(n) UART_REG(n, 1) /* High */ +#define UART_DLL(n) UART_REG(n, 0) /* Low */ +#define UART_DLH(n) UART_REG(n, 1) /* High */ /* MTK extension */ -#define UART_HIGHSPEED(n) UART_REG(n, 9) -#define UART_SAMPLE_COUNT(n) UART_REG(n, 10) -#define UART_SAMPLE_POINT(n) UART_REG(n, 11) -#define UART_RATE_FIX(n) UART_REG(n, 13) +#define UART_HIGHSPEED(n) UART_REG(n, 9) +#define UART_SAMPLE_COUNT(n) UART_REG(n, 10) +#define UART_SAMPLE_POINT(n) UART_REG(n, 11) +#define UART_RATE_FIX(n) UART_REG(n, 13) #endif /* __CROS_EC_SERIAL_REG_H */ |