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| author | Tzung-Bi Shih <tzungbi@chromium.org> | 2021-06-29 15:03:21 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-29 09:03:28 +0000 |
| commit | 61be90bd4004e4a3d412005f6d56b3188952504c (patch) | |
| tree | a46ffee0abdb63cbd442def9696a0e99c5bc9d79 /chip/mt_scp/mt8195 | |
| parent | c0c8292345b2d15fd69547b22e19bfc9917f4d77 (diff) | |
| download | chrome-ec-61be90bd4004e4a3d412005f6d56b3188952504c.tar.gz | |
chip/mt_scp: support MT8195 UART
Supports MT8195 UART.
BRANCH=none
BUG=b:189300514
TEST=make BOARD=cherry_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I948e0208f664de72de027357d4ba7336715e92fa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993789
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Diffstat (limited to 'chip/mt_scp/mt8195')
| -rw-r--r-- | chip/mt_scp/mt8195/uart.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/chip/mt_scp/mt8195/uart.c b/chip/mt_scp/mt8195/uart.c index 78e7903e08..e8d29cf311 100644 --- a/chip/mt_scp/mt8195/uart.c +++ b/chip/mt_scp/mt8195/uart.c @@ -16,4 +16,12 @@ void uart_init_pinmux(void) { +#if UARTN == 0 + SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_26M); + SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST; + + /* set AP GPIO102 and GPIO103 to alt func 5 */ + AP_GPIO_MODE12_CLR = 0x77000000; + AP_GPIO_MODE12_SET = 0x55000000; +#endif } |