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| author | Tzung-Bi Shih <tzungbi@chromium.org> | 2021-06-29 15:03:21 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-29 09:03:28 +0000 |
| commit | 61be90bd4004e4a3d412005f6d56b3188952504c (patch) | |
| tree | a46ffee0abdb63cbd442def9696a0e99c5bc9d79 /chip/mt_scp/rv32i_common | |
| parent | c0c8292345b2d15fd69547b22e19bfc9917f4d77 (diff) | |
| download | chrome-ec-61be90bd4004e4a3d412005f6d56b3188952504c.tar.gz | |
chip/mt_scp: support MT8195 UART
Supports MT8195 UART.
BRANCH=none
BUG=b:189300514
TEST=make BOARD=cherry_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I948e0208f664de72de027357d4ba7336715e92fa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993789
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Diffstat (limited to 'chip/mt_scp/rv32i_common')
| -rw-r--r-- | chip/mt_scp/rv32i_common/registers.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h index a64c446c8c..f4d03aa228 100644 --- a/chip/mt_scp/rv32i_common/registers.h +++ b/chip/mt_scp/rv32i_common/registers.h @@ -232,6 +232,8 @@ #define AP_GPIO_BASE (AP_REG_BASE + 0x5000) #define AP_GPIO_MODE11_SET REG32(AP_GPIO_BASE + 0x03B4) #define AP_GPIO_MODE11_CLR REG32(AP_GPIO_BASE + 0x03B8) +#define AP_GPIO_MODE12_SET REG32(AP_GPIO_BASE + 0x03C4) +#define AP_GPIO_MODE12_CLR REG32(AP_GPIO_BASE + 0x03C8) #define AP_GPIO_MODE20_SET REG32(AP_GPIO_BASE + 0x0444) #define AP_GPIO_MODE20_CLR REG32(AP_GPIO_BASE + 0x0448) /* |