diff options
| author | Rong Chang <rongchang@chromium.org> | 2019-02-22 16:14:18 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-03-16 01:53:23 -0700 |
| commit | 8f210f9384a1a268201d04f4b285ed519198cb09 (patch) | |
| tree | 40f57fb8d77f32e12dc59790f1b43e2e33c2bafa /chip/mt_scp | |
| parent | 787d34561f0a91b6565a9886887d60606c43f426 (diff) | |
| download | chrome-ec-8f210f9384a1a268201d04f4b285ed519198cb09.tar.gz | |
kukui: scp: set CPU clock to ULPOSC2
SCP CPU clock source can be sourced from 26MHz system clock, 32K low
speed clock, and 2 high speed sources ULPOSC1, ULPOSC2. ULPOSC2 is
enabled to run at 330MHz by default. This CL switch CPU to ULPOSC2 after
enabling the source.
BRANCH=none
BUG=b:125616659
TEST=manual
check current clock source using console command:
> rw 0x405C4000
read 0x405c4000 = 0x00000803
Change-Id: I11672e2eb5b5a3ebebdf2a21a6ebed83b4535ee5
Signed-off-by: Rong Chang <rongchang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1482631
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Diffstat (limited to 'chip/mt_scp')
| -rw-r--r-- | chip/mt_scp/registers.h | 5 | ||||
| -rw-r--r-- | chip/mt_scp/system.c | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h index 9c61a5dd2e..eb118f8409 100644 --- a/chip/mt_scp/registers.h +++ b/chip/mt_scp/registers.h @@ -241,6 +241,11 @@ /* Clock, PMIC wrapper, etc. */ #define SCP_CLK_BASE (SCP_CFG_BASE + 0x4000) #define SCP_CLK_SEL REG32(SCP_CLK_BASE) +#define CLK_SEL_SYS_26M 0 +#define CLK_SEL_32K 1 +#define CLK_SEL_ULPOSC_1 2 +#define CLK_SEL_ULPOSC_2 3 + #define SCP_CLK_EN REG32(SCP_CLK_BASE + 0x04) #define EN_CLK_SYS (1 << 0) /* System clock */ #define EN_CLK_HIGH (1 << 1) /* ULPOSC */ diff --git a/chip/mt_scp/system.c b/chip/mt_scp/system.c index 9a68fac27b..fa5ee4ec6b 100644 --- a/chip/mt_scp/system.c +++ b/chip/mt_scp/system.c @@ -191,6 +191,7 @@ void system_pre_init(void) scp_enable_tcm(); /* Clock */ scp_enable_clock(); + SCP_CLK_SEL = CLK_SEL_ULPOSC_2; /* Peripheral IRQ */ scp_enable_pirq(); /* Init dram mapping (and cache) */ |