diff options
author | CHLin <CHLin56@nuvoton.com> | 2020-09-29 14:23:59 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-10-13 11:29:46 +0000 |
commit | 0f12014ad53ddfd0063a733a1357f81478136dc8 (patch) | |
tree | b8a4e3b500ed7b9d28ae67588b8ceba42879503c /chip/npcx/clock.c | |
parent | 44435d3b9c447ad25edaa8aece42f1cff0dd6df9 (diff) | |
download | chrome-ec-0f12014ad53ddfd0063a733a1357f81478136dc8.tar.gz |
npcx9: support SHA256 hardware accelerator
There is the hardware accelerator for SHA computation inside npcx9. This
CL wraps the Nuvoton SHA library APIs (which are in the ROM) to Chromium
EC's SHA256_* APIs to speed up the SHA256 computation.
With the help of the hardware accelerator, the hash computation runs
several times faster than the software method (see b:155771688 for more
detailed evaluation data.) Also, we can gain ~840 bytes of code size.
BRANCH=none
BUG=b:165777478
BUG=b:155771688
TEST=pass "make buildall"
TEST=flash the same RW image; #define/#undef CONFIG_SHA256_HW_ACCELERATE
; verify the RW hash value is the same in the console message.
TEST=with the following test CL, move test patterns in test/sha256.c
to board/npcx9_evb/test_sha256.c; pass all test patterns.
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I45ca609889bd73573d67d15f3e561614201e60f6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2455021
Tested-by: CH Lin <chlin56@nuvoton.com>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
Diffstat (limited to 'chip/npcx/clock.c')
-rw-r--r-- | chip/npcx/clock.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c index 0f8f737401..ad611973be 100644 --- a/chip/npcx/clock.c +++ b/chip/npcx/clock.c @@ -166,11 +166,20 @@ void clock_turbo(void) #elif NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7 void clock_turbo(void) { - /* +#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX9 + /* For NPCX9: + * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since + * CORE_CLK > 66MHz, we also need to set FIUDIV as 1 but + * can keep AHB6DIV to 0. + */ + NPCX_HFCGP = 0x00; +#else + /* For NPCX7: * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1. */ NPCX_HFCGP = 0x01; +#endif NPCX_HFCBCD = BIT(4); } |