npcx: Better download time for sysjump by increasing clock freq.

In order to improve the performance of sysjump, the CL increases the clock
freq of ec to 50M HZ (The maximum freq rate for SPI flash.). Once ec jumps
into the other region successfully, the clock freq is restored to the
default value (15MHz) in main routine.

Modified sources:
1. clock.c: Add clock_turbo for speed up clock's freq to max.
2. clock_chip.h: The declarartion for clock_turbo.
3. system.c: Speed up clock rate before downloading FW.

BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=npcx_evb; test nuvoton IC specific drivers

Change-Id: I996e35fff336e6292599497feb1ee6c2f95becba
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/381799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 28 insertions, 0 deletions

diff --git a/chip/npcx/clock.c b/chip/npcx/clock.c
index f6a65cb02f..044afad142 100644
--- a/chip/npcx/clock.c
+++ b/chip/npcx/clock.c
@@ -164,6 +164,34 @@ void clock_init(void)
 	gpio_config_module(MODULE_CLOCK, 1);
 }
 
+
+/**
+ * Set the CPU clock to maximum freq for better performance.
+ */
+void clock_turbo(void)
+{
+	/* Configure Frequency multiplier values to 50MHz */
+	NPCX_HFCGN  = 0x02;
+	NPCX_HFCGML = 0xEC;
+	NPCX_HFCGMH = 0x0B;
+
+	/* Load M and N values into the frequency multiplier */
+	SET_BIT(NPCX_HFCGCTRL, NPCX_HFCGCTRL_LOAD);
+
+	/* Wait for stable */
+	while (IS_BIT_SET(NPCX_HFCGCTRL, NPCX_HFCGCTRL_CLK_CHNG))
+		;
+
+	/* Keep Core CLK & FMCLK are the same if Core CLK exceed 33MHz */
+	NPCX_HFCGP = 0x00;
+
+	/*
+	 * Let APB2 equals Core CLK/2 if default APB2 clock is divisible
+	 * by 1MHz
+	 */
+	NPCX_HFCBCD = NPCX_HFCBCD & 0xF3;
+}
+
 /**
  * Return the current clock frequency in Hz.
  */