diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2020-06-02 13:59:57 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-06-02 23:46:21 +0000 |
| commit | 5ae7720ca6599c89ad54614b36af5269340fe2fd (patch) | |
| tree | 8eec25d87f869c42130319120457eebdd2e40ace /chip/npcx/config_chip-npcx5.h | |
| parent | 724144b3edc1909f39c6cd634daa90a63c3134b0 (diff) | |
| download | chrome-ec-5ae7720ca6599c89ad54614b36af5269340fe2fd.tar.gz | |
fizz: remove board from cr50_stab
Not sure why this board was kept in, probably because fizz was mixed
up with fuzz.
BUG=none
TEST='make buildall -j' succeeds
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Change-Id: I4b08333d12bdfe8001b7e1c2b7c5860aef947a22
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2227168
Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org>
Diffstat (limited to 'chip/npcx/config_chip-npcx5.h')
| -rw-r--r-- | chip/npcx/config_chip-npcx5.h | 70 |
1 files changed, 0 insertions, 70 deletions
diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h deleted file mode 100644 index e1ad4923b8..0000000000 --- a/chip/npcx/config_chip-npcx5.h +++ /dev/null @@ -1,70 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ -#ifndef __CROS_EC_CONFIG_CHIP_NPCX5_H -#define __CROS_EC_CONFIG_CHIP_NPCX5_H - -/* - * NPCX5 Series Device-Specific Information - * Ex. NPCX5(M)(N)(G) - * @param M: 7: 132-pins package, 8: 128-pins package - * @param N: 5: 128KB RAM Size, 6: 256KB RAM Size - * @param G: Google EC. - */ - -/*****************************************************************************/ -/* Hardware features */ - -/* Number of UART modules. */ -#define UART_MODULE_COUNT 1 - -/* - * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one - * additional port. - */ -#define CONFIG_I2C_MULTI_PORT_CONTROLLER -/* Number of I2C controllers */ -#define I2C_CONTROLLER_COUNT 4 -/* Number of I2C ports */ -#define I2C_PORT_COUNT 5 - -/*****************************************************************************/ -/* Memory mapping */ -#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ -#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ -#define CONFIG_DATA_RAM_SIZE 0x00008000 /* Size of data RAM */ -#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) -#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ - -/* Use chip variant to specify the size and start address of program memory */ -#if defined(CHIP_VARIANT_NPCX5M5G) -/* 96KB RAM for FW code */ -#define NPCX_PROGRAM_MEMORY_SIZE (96 * 1024) -/* program memory base address for 96KB Code RAM (ie. 0x100C0000 - 96KB) */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000 -#elif defined(CHIP_VARIANT_NPCX5M6G) -/* 224KB RAM for FW code */ -#define NPCX_PROGRAM_MEMORY_SIZE (224 * 1024) -/* program memory base address for 224KB Code RAM (ie. 0x100C0000 - 224KB) */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x10088000 -#else -#error "Unsupported chip variant" -#endif - -/* Total RAM size checking for npcx ec */ -#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE) -#if defined(CHIP_VARIANT_NPCX5M5G) -/* 128KB RAM in NPCX5M5G */ -#if (NPCX_RAM_SIZE != 0x20000) -#error "Wrong memory mapping layout for NPCX5M5G" -#endif -#elif defined(CHIP_VARIANT_NPCX5M6G) -/* 256KB RAM in NPCX5M6G */ -#if (NPCX_RAM_SIZE != 0x40000) -#error "Wrong memory mapping layout for NPCX5M6G" -#endif -#endif - -#endif /* __CROS_EC_CONFIG_CHIP_NPCX5_H */ |