diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2017-08-01 12:41:13 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-08-07 19:29:13 -0700 |
| commit | 5f72f0a085f4b3063e119d629fe3b20c4961317f (patch) | |
| tree | c06b8e38c7b5de242e8de7a0375ae33672d0764a /chip/npcx/config_chip-npcx5.h | |
| parent | 0d385e7e5754327dae713415d3b931172514eae9 (diff) | |
| download | chrome-ec-5f72f0a085f4b3063e119d629fe3b20c4961317f.tar.gz | |
npcx: Define CONFIG_DATA_RAM_SIZE
This patch defines CONFIG_DATA_RAM_SIZE, which indicates the size
of the RAM used for data, thus can be marked as non-executable.
If it's not defined, it defaults to CONFIG_RAM_SIZE. Thus, other chips
are not affected.
BUG=b:36037354
BRANCH=none
TEST=buildall. Run 'sysjump disable' on Reef and verify mpu_protect_ram
is successful.
Change-Id: I54d74fd1dabff7e1013fff2542fd02c3646803d1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/596518
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'chip/npcx/config_chip-npcx5.h')
| -rw-r--r-- | chip/npcx/config_chip-npcx5.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/chip/npcx/config_chip-npcx5.h b/chip/npcx/config_chip-npcx5.h index 71c8d8d7af..98ea716646 100644 --- a/chip/npcx/config_chip-npcx5.h +++ b/chip/npcx/config_chip-npcx5.h @@ -27,11 +27,12 @@ /*****************************************************************************/ /* Memory mapping */ -#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ -#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ -#define CONFIG_RAM_SIZE (0x0008000 - NPCX_BTRAM_SIZE) /* 30KB data ram */ -#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ +#define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +#define CONFIG_DATA_RAM_SIZE 0x00008000 /* Size of data RAM */ +#define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) +#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ +#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ /* Use chip variant to specify the size and start address of program memory */ #if defined(CHIP_VARIANT_NPCX5M5G) @@ -49,8 +50,7 @@ #endif /* Total RAM size checking for npcx ec */ -#define NPCX_RAM_SIZE (NPCX_BTRAM_SIZE + CONFIG_RAM_SIZE + \ - NPCX_PROGRAM_MEMORY_SIZE) +#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE) #if defined(CHIP_VARIANT_NPCX5M5G) /* 128KB RAM in NPCX5M5G */ #if (NPCX_RAM_SIZE != 0x20000) |