diff options
| author | CHLin <CHLIN56@nuvoton.com> | 2018-11-19 15:09:09 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-11-28 05:29:31 -0800 |
| commit | 7491fb02976c649d186d79299bb76b8974c02521 (patch) | |
| tree | 506a14b6a6c28a1cdcb4dfa734f5762e7253b8e5 /chip/npcx/config_chip-npcx7.h | |
| parent | 9fd39f0e58ac10abd2e8ae0f0d2734f27776d03e (diff) | |
| download | chrome-ec-7491fb02976c649d186d79299bb76b8974c02521.tar.gz | |
npcx: introduce npcx7m6fc chip definitions and configurations
This CL includes:
1. add CHIP_VARIANT_NPCX7M6FC in the npcx chip configuration files to
define what (RAM, features...) is supported in npcx7m6fc.
2. add the chip id and chip revision id of npcx7m6fc.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=Change CHIP_VARIANT to npcx7m6fc in board/npcx7_evb/build.mk;
flash image in the internal testing board of npcx7m6fc; make sure the
EC can boot up. Check the chip ID and chip revision ID are correct by
console command "version".
TEST=build and flash the yorp image to the platform; make sure no issues
are found.
Change-Id: Ibcb25fc09b21ec3e5738418af16826035ec81e69
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1343639
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'chip/npcx/config_chip-npcx7.h')
| -rw-r--r-- | chip/npcx/config_chip-npcx7.h | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h index 7ca1e2257f..a932fa5836 100644 --- a/chip/npcx/config_chip-npcx7.h +++ b/chip/npcx/config_chip-npcx7.h @@ -20,13 +20,14 @@ /* The optional hardware features depend on chip variant */ #if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ - defined(CHIP_VARIANT_NPCX7M7WB) + defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7WB) #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */ #define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */ #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */ #endif -#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M7WB) +#if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \ + defined(CHIP_VARIANT_NPCX7M7WB) #define NPCX_UART_FIFO_SUPPORT /* Number of UART modules. */ #define NPCX_SECOND_UART @@ -60,14 +61,14 @@ /* Memory mapping */ #define NPCX_BTRAM_SIZE 0x800 /* 2KB data ram used by booter. */ #define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ -/* 63KB data RAM */ +/* 62 KB data RAM + 2 KB BT RAM size */ #define CONFIG_DATA_RAM_SIZE 0x00010000 #define CONFIG_RAM_SIZE (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE) /* no low power ram in npcx7 series */ /* Use chip variant to specify the size and start address of program memory */ #if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ - defined(CHIP_VARIANT_NPCX7M6G) + defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) /* 192KB RAM for FW code */ #define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024) /* program memory base address for 192KB Code RAM (ie. 0x100C0000 - 192KB) */ @@ -84,15 +85,15 @@ /* Total RAM size checking for npcx ec */ #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE) #if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \ - defined(CHIP_VARIANT_NPCX7M6G) -/* 256KB RAM in NPCX7M6F/NPCX7M6G/NPCX7M6FB */ + defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) +/* 256KB RAM in NPCX7M6F/NPCX7M6FB/NPCX7M6FC/NPCX7M6G */ #if (NPCX_RAM_SIZE != 0x40000) #error "Wrong memory mapping layout for NPCX7M6F" #endif #elif defined(CHIP_VARIANT_NPCX7M7WB) /* 384KB RAM in NPCX7M7WB */ #if (NPCX_RAM_SIZE != 0x60000) -#error "Wrong memory mapping layout for NPCX7M6F" +#error "Wrong memory mapping layout for NPCX7M7W" #endif #endif |