Merge remote-tracking branch cros/main into firmware-fpmcu-dartmonkey-releasefirmware-fpmcu-dartmonkey-release

Generated by: ./util/update_release_branch.py --board dartmonkey --relevant_paths_file
./util/fingerprint-relevant-paths.txt firmware-fpmcu-dartmonkey-release

Relevant changes:

git log --oneline 6c1587ca70..28712dae9d -- board/nocturne_fp
board/dartmonkey common/fpsensor docs/fingerprint driver/fingerprint
util/getversion.sh

ded9307b79 util/getversion.sh: Fix version when not in a git repo
956055e692 board: change Google USB vendor info
71b2ef709d Update license boilerplate text in source code files
33e11afda0 Revert "fpsensor: Build fpsensor source file with C++"
c8d0360723 fpsensor: Build fpsensor source file with C++
bc113abd53 fpsensor: Fix g++ compiler error
150a58a0dc fpsensor: Fix fp_set_sensor_mode return type
b33b5ce85b fpsensor: Remove nested designators for C++ compatibility
2e864b2539 tree-wide: const-ify argv for console commands
56d8b360f9 test: Add test for get ikm failure when seed not set
3a3d6c3690 test: Add test for fpsensor trivial key failure
233e6bbd08 fpsensor_crypto: Abstract calls to hmac_SHA256
0a041b285b docs/fingerprint: Typo correction
c03fab67e2 docs/fingerprint: Fix the path of fputils.py
0b5d4baf5a util/getversion.sh: Fix empty file list handling
6e128fe760 FPMCU dev board environment with Satlab
3eb29b6aa5 builtin: Move ssize_t to sys/types.h
345d62ebd1 docs/fingerprint: Update power numbers for latest dartmonkey release
c25ffdb316 common: Conditionally support printf %l and %i modifiers
9a3c514b45 test: Add a test to check if the debugger is connected
54e603413f Move standard library tests to their own file
43fa6b4bf8 docs/fingerprint: Update power numbers for latest bloonchipper release
25536f9a84 driver/fingerprint/fpc/bep/fpc_sensor_spi.c: Format with clang-format
4face99efd driver/fingerprint/fpc/libfp/fpc_sensor_pal.h: Format with clang-format
738de2b575 trng: Rename rand to trng_rand
14b8270edd docs/fingerprint: Update dragonclaw power numbers
0b268f93d1 driver/fingerprint/fpc/libfp/fpc_private.c: Format with clang-format
f80da163f2 driver/fingerprint/fpc/libfp/fpc_private.h: Format with clang-format
a0751778f4 board/nocturne_fp/ro_workarounds.c: Format with clang-format
5e9c85c9b1 driver/fingerprint/fpc/libfp/fpc_sensor_pal.c: Format with clang-format
c1f9dd3cf8 driver/fingerprint/fpc/libfp/fpc_bio_algorithm.h: Format with clang-format
eb1e1bed8d driver/fingerprint/fpc/libfp/fpc1145_private.h: Format with clang-format
6e7b611821 driver/fingerprint/fpc/bep/fpc_bio_algorithm.h: Format with clang-format
e0589cd5e2 driver/fingerprint/fpc/bep/fpc1035_private.h: Format with clang-format
58f0246dbe board/nocturne_fp/board_ro.c: Format with clang-format
7905e556a0 common/fpsensor/fpsensor_crypto.c: Format with clang-format
21289d170c driver/fingerprint/fpc/bep/fpc1025_private.h: Format with clang-format
98a20f937e common/fpsensor/fpsensor_state.c: Format with clang-format
a2d255d8af common/fpsensor/fpsensor.c: Format with clang-format
84e53a65da board/nocturne_fp/board.h: Format with clang-format
73055eeb3f driver/fingerprint/fpc/bep/fpc_private.c: Format with clang-format
0f7b5cb509 common/fpsensor/fpsensor_private.h: Format with clang-format
1ceade6e65 driver/fingerprint/fpc/bep/fpc_private.h: Format with clang-format
dca9d74321 Revert "trng: Rename rand to trng_rand"
a6b0b3554f trng: Rename rand to trng_rand
28d0b75b70 third_party/boringssl: Remove unused header

BRANCH=None
BUG=b:244387210 b:242720240 b:215613183 b:242720910 b:236386294
BUG=b:234181908 b:244781166 b:234781655 b:234143158 b:234181908
BUG=b:237344361 b:236025198 b:234181908 b:180945056 chromium:1098010
BUG=b:246424843 b:234181908 b:131913998
TEST=`make -j buildall`
TEST=./util/run_device_tests.py --board dartmonkey
     Test "aes": PASSED
     Test "cec": PASSED
     Test "cortexm_fpu": PASSED
     Test "crc": PASSED
     Test "flash_physical": PASSED
     Test "flash_write_protect": PASSED
     Test "fpsensor_hw": PASSED
     Test "fpsensor_spi_ro": PASSED
     Test "fpsensor_spi_rw": PASSED
     Test "fpsensor_uart_ro": PASSED
     Test "fpsensor_uart_rw": PASSED
     Test "mpu_ro": PASSED
     Test "mpu_rw": PASSED
     Test "mutex": PASSED
     Test "pingpong": PASSED
     Test "printf": PASSED
     Test "queue": PASSED
     Test "rollback_region0": PASSED
     Test "rollback_region1": PASSED
     Test "rollback_entropy": PASSED
     Test "rtc": PASSED
     Test "sha256": PASSED
     Test "sha256_unrolled": PASSED
     Test "static_if": PASSED
     Test "stdlib": PASSED
     Test "system_is_locked_wp_on": PASSED
     Test "system_is_locked_wp_off": PASSED
     Test "timer_dos": PASSED
     Test "utils": PASSED
     Test "utils_str": PASSED
     Test "panic_data_dartmonkey_v2.0.2887": PASSED
     Test "panic_data_nocturne_fp_v2.2.64": PASSED
     Test "panic_data_nami_fp_v2.2.144": PASSED
Force-Relevant-Builds: all
Signed-off-by: Tom Hughes <tomhughes@chromium.org>

Change-Id: I2c312583a709fedae8fe11d92c22328c3b634bc7

1 files changed, 35 insertions, 36 deletions

diff --git a/chip/npcx/config_chip-npcx9.h b/chip/npcx/config_chip-npcx9.h
index 7f154dbe42..736aef8a1c 100644
--- a/chip/npcx/config_chip-npcx9.h
+++ b/chip/npcx/config_chip-npcx9.h
@@ -1,4 +1,4 @@
-/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+/* Copyright 2020 The ChromiumOS Authors
  * Use of this source code is governed by a BSD-style license that can be
  * found in the LICENSE file.
  */
@@ -16,8 +16,8 @@
  */
 
 /* Chip ID for all variants */
-#define NPCX996F_CHIP_ID		0x21
-#define NPCX993F_CHIP_ID		0x25
+#define NPCX996F_CHIP_ID 0x21
+#define NPCX993F_CHIP_ID 0x25
 
 /*****************************************************************************/
 /* Hardware features */
@@ -25,7 +25,8 @@
 #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
 #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
 #define NPCX_LCT_SUPPORT /* Long Countdown Timer support */
-#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
+#define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power \
+			       */
 
 #define NPCX_UART_FIFO_SUPPORT
 /* Number of UART modules. */
@@ -55,10 +56,10 @@
 
 /* PSL_OUT optional configuration */
 /* Set PSL_OUT mode to pulse mode */
-#define NPCX_PSL_CFG_PSL_OUT_PULSE	BIT(0)
+#define NPCX_PSL_CFG_PSL_OUT_PULSE BIT(0)
 /* set PSL_OUT to open-drain */
-#define NPCX_PSL_CFG_PSL_OUT_OD		BIT(1)
-#define CONFIG_HIBERNATE_PSL_OUT_FLAGS	0
+#define NPCX_PSL_CFG_PSL_OUT_OD BIT(1)
+#define CONFIG_HIBERNATE_PSL_OUT_FLAGS 0
 
 /*
  * Workaound the issue 3.10 in the NPCX99nF errata rev1.2
@@ -75,36 +76,35 @@
 #define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE)
 
 #if defined(CHIP_VARIANT_NPCX9M3F)
-	/*
-	 * 256KB program RAM, but only 512K of Flash. After the boot header is
-	 * added, a 256K image would be too large to fit in either RO or RW
-	 * sections of Flash (each of which is half of it). Because other code
-	 * assumes that image size is a multiple of Flash erase granularity, we
-	 * sacrifice a whole sector.
-	 */
-#	define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000)
-	/* program memory base address for Code RAM (0x100C0000 - 256KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10080000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* Two blocks of data RAM - total size is 64KB */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#	define CONFIG_RAM_SIZE         CONFIG_DATA_RAM_SIZE
-
-	/* Override default NPCX_RAM_SIZE because we're excluding a block. */
-#	undef NPCX_RAM_SIZE
-#	define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + \
-			      NPCX_PROGRAM_MEMORY_SIZE + 0x1000)
+/*
+ * 256KB program RAM, but only 512K of Flash. After the boot header is
+ * added, a 256K image would be too large to fit in either RO or RW
+ * sections of Flash (each of which is half of it). Because other code
+ * assumes that image size is a multiple of Flash erase granularity, we
+ * sacrifice a whole sector.
+ */
+#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024 - 0x1000)
+/* program memory base address for Code RAM (0x100C0000 - 256KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10080000
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+/* Two blocks of data RAM - total size is 64KB */
+#define CONFIG_DATA_RAM_SIZE 0x00010000
+#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE
+
+/* Override default NPCX_RAM_SIZE because we're excluding a block. */
+#undef NPCX_RAM_SIZE
+#define NPCX_RAM_SIZE (CONFIG_DATA_RAM_SIZE + NPCX_PROGRAM_MEMORY_SIZE + 0x1000)
 #elif defined(CHIP_VARIANT_NPCX9M6F)
-	/* 192KB RAM for FW code */
-#	define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
-	/* program memory base address for Code RAM (0x100C0000 - 192KB) */
-#	define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#	define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
-	/* Two blocks of data RAM - total size is 64KB */
-#	define CONFIG_DATA_RAM_SIZE    0x00010000
-#	define CONFIG_RAM_SIZE         CONFIG_DATA_RAM_SIZE
+/* 192KB RAM for FW code */
+#define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
+/* program memory base address for Code RAM (0x100C0000 - 192KB) */
+#define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
+#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */
+/* Two blocks of data RAM - total size is 64KB */
+#define CONFIG_DATA_RAM_SIZE 0x00010000
+#define CONFIG_RAM_SIZE CONFIG_DATA_RAM_SIZE
 #else
-#	error "Unsupported chip variant"
+#error "Unsupported chip variant"
 #endif
 
 /* Internal spi-flash setting */
@@ -112,5 +112,4 @@
 #define CONFIG_SPI_FLASH_W25Q40 /* Internal spi flash type */
 #define CONFIG_FLASH_SIZE_BYTES 0x00080000 /* 512 KB internal spi flash */
 
-
 #endif /* __CROS_EC_CONFIG_CHIP_NPCX9_H */