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| author | Steven Jian <steven.jian@intel.com> | 2015-04-01 01:25:42 +0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-05-27 03:58:16 +0000 |
| commit | 937cc8a64e5971def21303e7a19a4ad9553e0ace (patch) | |
| tree | 321543152e0c4d61e686ca7b92edd0d027bb168b /chip/npcx/config_chip.h | |
| parent | e216906c9327655d71b8758b7f11c2f744e55018 (diff) | |
| download | chrome-ec-937cc8a64e5971def21303e7a19a4ad9553e0ace.tar.gz | |
mec1322: Simplify GPIO lists
Our existing GPIO macros use port# / gpio#, but the concept of different
GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros
for chips which do not have distinct GPIO ports.
BUG=None
BRANCH=None
TEST=make buildall -j
Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b
Signed-off-by: Steven Jian <steven.jian@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/262841
Reviewed-by: Anton Staaf <robotboy@chromium.org>
Diffstat (limited to 'chip/npcx/config_chip.h')
| -rw-r--r-- | chip/npcx/config_chip.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 272c5eebed..cd951e1f22 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -110,4 +110,7 @@ /* Compile for running from RAM instead of flash */ /* #define COMPILE_FOR_RAM */ +#define GPIO_PIN(port, index) GPIO_##port, (1 << index) +#define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) + #endif /* __CROS_EC_CONFIG_CHIP_H */ |