diff options
| author | Mulin Chao <mlchao@nuvoton.com> | 2017-04-18 11:10:41 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2017-04-25 01:45:37 -0700 |
| commit | 9cd1dcc3fd581100d28444c087f3df0ca8a8e0d6 (patch) | |
| tree | b4d369d84e8df9259ad1eac10fe24301f1f00dee /chip/npcx/config_chip.h | |
| parent | 5eaf807dcdbc023d2d2cf12d6d150ca7b7b2fb9f (diff) | |
| download | chrome-ec-9cd1dcc3fd581100d28444c087f3df0ca8a8e0d6.tar.gz | |
npcx: Introduce npcx7 series ec chip definitions and configurations.
This CL includes:
1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish
which npcx's ec is used on the board.
2. Add config_chip-npcx5/7.h files and move features depend on chip
family into them.
3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and
NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on
npcx7 ec. We'll use them later in gpio/system/flash drivers.
4. Add ram size checking for all npcx ec series.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series (besides gru).
Build poppy board and upload FW to platform. No issues found.
Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/481560
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/config_chip.h')
| -rw-r--r-- | chip/npcx/config_chip.h | 45 |
1 files changed, 9 insertions, 36 deletions
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 1442a58d50..90bfc9ab44 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -9,6 +9,15 @@ /* CPU core BFD configuration */ #include "core/cortex-m/config_core.h" +/* Features depend on chip family */ +#if defined(CHIP_FAMILY_NPCX5) +#include "config_chip-npcx5.h" +#elif defined(CHIP_FAMILY_NPCX7) +#include "config_chip-npcx7.h" +#else +#error "Unsupported chip family" +#endif + /* 32k hz internal oscillator frequency (FRCLK) */ #define INT_32K_CLOCK 32768 @@ -26,42 +35,6 @@ #define HOOK_TICK_INTERVAL_MS 200 #define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC) -/* - * Number of I2C controllers. Controller 0 has 2 ports, so the chip has one - * additional port. - */ -#define CONFIG_I2C_MULTI_PORT_CONTROLLER -/* Number of I2C controllers */ -#define I2C_CONTROLLER_COUNT 4 -/* Number of I2C ports */ -#define I2C_PORT_COUNT 5 - - -/* Number of PWM ports */ -#define PWM_COUNT 8 - -/*****************************************************************************/ -/* Memory mapping */ -#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ -#define CONFIG_RAM_SIZE (0x00008000 - 0x800) /* 30KB data ram */ -#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ - -/* Use chip variant to specify the size and start address of program memory */ -#if defined(CHIP_VARIANT_NPCX5M5G) -/* 96KB RAM for FW code */ -#define NPCX_PROGRAM_MEMORY_SIZE (96 * 1024) -/* program memory base address for 128KB RAM */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000 -#elif defined(CHIP_VARIANT_NPCX5M6G) -/* 224KB RAM for FW code */ -#define NPCX_PROGRAM_MEMORY_SIZE (224 * 1024) -/* program memory base address for 256KB RAM */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x10088000 -#else -#error "Unsupported chip variant" -#endif - /* System stack size */ #define CONFIG_STACK_SIZE 1024 |