diff options
| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-04 19:09:33 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-16 14:49:31 -0700 |
| commit | d58e54730c03290296df5bb65cb84264e4b2facc (patch) | |
| tree | d736570c84a0e9737b8881ec68b073327a5c2ae5 /chip/npcx/config_chip.h | |
| parent | 4b3c13ddfefd229dde49fb4cbf5a6bfc49f64973 (diff) | |
| download | chrome-ec-d58e54730c03290296df5bb65cb84264e4b2facc.tar.gz | |
cleanup: Rename geometry constants
Rename and add geometry constants to match spec doc -
https://goo.gl/fnzTvr.
CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE
CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE
Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and
CONFIG_MAPPED_STORAGE_BASE where appropriate.
This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up
CL.
BRANCH=None
BUG=chrome-os-partner:23796
TEST=With entire patch series, on both Samus and Glados:
- Verify 'version' EC console command is correct
- Verify 'flashrom -p ec -r read.bin' reads back EC image
- Verify software sync correctly flashes both EC and PD RW images
Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/297484
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Diffstat (limited to 'chip/npcx/config_chip.h')
| -rw-r--r-- | chip/npcx/config_chip.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 6bb5809235..56db32cc65 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -45,13 +45,13 @@ /*****************************************************************************/ /* Memory mapping */ -#define CONFIG_RAM_BASE 0x200C0000 /* memory map address of data ram */ -#define CONFIG_RAM_SIZE (0x00008000 - 0x800) /* 30KB data ram */ -#define CONFIG_CDRAM_BASE 0x100A8000 /* memory map address of code ram */ -#define CONFIG_CDRAM_SIZE 0x00018000 /* 96KB code ram */ -#define CONFIG_FLASH_BASE 0x64000000 /* memory address of spi-flash */ -#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of low power ram */ -#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ +#define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ +#define CONFIG_RAM_SIZE (0x00008000 - 0x800) /* 30KB data ram */ +#define CONFIG_CDRAM_BASE 0x100A8000 /* memory address of code ram */ +#define CONFIG_CDRAM_SIZE 0x00018000 /* 96KB code ram */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x64000000 /* program memory base address */ +#define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ +#define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ /* System stack size */ #define CONFIG_STACK_SIZE 4096 |